Nokia Corporation

Xilinx, Inc.

Future Wei Technologies, Inc.

Core Wireless Licensing S.a.r.l.

Other

Nokia Telecommunications Oy

Joseph R Cavallaro

Christopher H Dick

Kiarash Amiri

Yuanbin Guo

Jorma Lilleberg

Raghavendar Mysore Rao

Michael Wu

Yang Sun

Dennis McCain

Bei Yin

Marjan Karkooti

Alexandre De Baynast

Predrag Radosavljevic

Jianzhong Zhang

Gilles Charbit

Gang Xu

Gabor T Szabo

Christoph Emanuel Studer

Frank K Tittel

Behnaam Aazhang

Motoi Kido

Aida Vosoughi

Guohui Wang

A LDPC decoder utilizes a new schedule that breaks a dependency between data of different layers of a parity check matrix, so that the forward scan in the next layer can begin to perform after a predetermined time has elapsed (i.e. a delay) since the backwards scan of the previous layer has begun, and before the backwards scan of the previous layer is completed. Accordingly, the computation at the next layer can begin as soon as possible.

High throughput low-density parity-check (LDPC) decoder via rescheduling

An apparatus relating generally to matrix inversion is disclosed. This apparatus includes a matrix inversion module coupled to receive matrix information and to provide an approximation of an inversion of the matrix information. The matrix inversion module comprises a decomposition block coupled to receive the matrix information and to decompose the matrix information into diagonal matrix information and off diagonal matrix information, and an expansion block. The expansion block is coupled to receive the diagonal matrix information and the off diagonal matrix information, and to invert a matrix sum of the diagonal matrix information and the off diagonal matrix information by generation of a portion of a series expansion.

Matrix inversion

The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix

A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.

Method and device for inter-chip and inter-antenna interference cancellation

A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

System and method for contention-free memory access

An apparatus for trellis-based detection in a communication system including a processor and memory having computer program code configured to construct a trellis representing a transmitted signal formed from a plurality of symbols, each having a constellation size, transmitted by a number of transmit antennas, and form a log likelihood ratio at nodes of the trellis as a log-sum of a number of exponential terms corresponding to a hypothesized transmitted bit value of the plurality of symbols. The number of exponential terms is limited by a number of most likely paths of the trellis extending from each node of the trellis and the constellation size. The processor and memory including computer program code are further configured to form a list at each node of the trellis of a size limited to the number of the most likely paths of the trellis extending from each node of the trellis.

Apparatus and method for trellis-based detection in a communication system

In accordance with an example embodiment of the present invention, an apparatus comprising: at least one processor; and at least one memory including computer program code, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus to perform at least the following: receiving a MIMO (multiple-input multiple output) encoded symbol vector, the symbol vector encoding a plurality of streams of a source node; estimating channel matrix between the source node and the apparatus; re-ordering columns in said channel matrix; determining a plurality of feedback bits based at least in part on the re-ordered channel matrix, wherein each bit of the feedback bits indicates detection or no detection of the corresponding antenna streams of the source node; and transmitting the feedback bits.

Method and apparatus for ordered partial detection with MIMO cooperation

An apparatus for trellis-based detection in a communication system including a processor and memory having computer program code configured to construct a trellis representing a transmitted signal formed from a plurality of symbols, each having a constellation size, transmitted by a number of transmit antennas, and form a log likelihood ratio at nodes of the trellis as a log-sum of a number of exponential terms including a priori information corresponding to a hypothesized transmitted bit value of the plurality of symbols. The number of exponential terms is limited by a number of most likely paths of the trellis extending from each node of the trellis and the constellation size. The processor and memory including computer program code are configured to form a list at each node of the trellis of a size limited to the number of the most likely paths of the trellis extending from each node.

A circuit detects symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A distance block for an initial transmitting antenna in an ordering of the transmitting antennas determines a distance value for each symbol in a constellation. A selector block selects a limited number of candidates for the initial transmitting antenna from the symbols having smaller distance values. For each first and successive second transmitting antenna in the ordering, a distance-selector block selects a candidate for the second transmitting antenna for each candidate for the first transmitting antenna. The candidate for the second transmitting antenna is a pairing having a smaller distance value among the pairings of the candidate for the first transmitting antenna and the symbols. An identifier block selects a last candidate having a smaller distance value among the candidates for a last transmitting antenna in the ordering. The last candidate includes the detected symbols.

Detector using limited symbol candidate generation for MIMO communication systems

A source sends an encoded data block during a first time interval to a destination and to a relay. The source sends additional parity bits for the encoded data block during a second time interval. The relay partially decodes that encoded data block to a process-defined end point (typically only a partial decoding), such as a fixed number of decoding iterations. After partial decoding the relay forms a modified data block having corrected information bits and the parity bits of the block it received, and sends the modified data block to the destination, during the second time interval. The destination decodes to a results-defined end point the modified data block it received from the relay using the additional parity bits it received from the source. If that end-point cannot be reached, the destination may begin anew decoding the original encoded data block it received from the source.

Distributed iterative decoding for co-operative diversity

Circuits detect communications from multiple transmitting antennas to multiple receiving antennas. A respective first block for each non-initial transmitting antenna determines partial distances for pairings of a first candidate and a quadrature-phase amplitude. A respective second block for the initial transmitting antenna determines partial distances for combinations of phase amplitudes. A respective second block for each non-initial transmitting antenna determines partial distances for pairings of a second candidate and an in-phase amplitude. A respective first selector for each non-initial transmitting antenna selects the first candidates from the pairings for the respective second block having smaller partial distances. A respective second selector for each non-initial transmitting antenna selects the second candidates from the pairings for the respective first block having smaller partial distances. An identifier circuit selects a final candidate with a smaller partial distance from the pairings of the respective second block for the last transmitting antenna.

Detecting in-phase and quadrature-phase amplitudes of MIMO communications

Circuits are provided for detecting symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A circuit includes distance blocks, selectors, and an identifier block. Each distance-block includes at least one sub-block, and each sub-block inputs a candidate for a corresponding transmitting antenna. The sub-block determines partial distances for pairings of the candidate and each symbol in a constellation from a partial distance of the candidate and signals received at the receiving antennas. At least one selector assigns each pairing for each candidate for a corresponding transmitting antenna to a bin having a range that includes the partial distance of the pairing. The selector selects candidates for a successive transmitting antenna from the bins having the smaller ranges. The identifier block selects a final candidate that is one of the pairings for a last transmitting antenna having a smaller partial distance.

Symbol detection in a MIMO communication system

A circuit detects symbols communicated between multiple transmitting antennas and multiple receiving antennas (MIMO). Distance blocks are coupled in a sequence according to an ordering of the transmitting antennas. The respective distance block associated with each transmitting antenna determines a distance value for each pairing of one or more candidates and a symbol in a constellation. A respective selector block is coupled between each successive pair of distance blocks in the sequence. The respective selector block selects the one or more candidates for the successive distance block as a limited number of the pairings having smaller ones of the distance values. A limit block coupled to the selector blocks provides the limited number to each selector block. An identifier block selects the pairing having a smaller one of the distance values from the last distance block in the sequence.

Limiting candidates for symbol detection in a MIMO communication system

A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.

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Pearland, TX, United States of America

Joseph R Cavallaro