International Business Machines Corporation

Joseph R Cavaliere

Richard R Konian

James L Walsh

Robert Otto Schwenker

Hans S Rupprecht

Robert A Henle

Rocco J Robortaccio

Gerard J Ashton

Cheng Tzong Horng

Narasipur G Anantha

Herbert I Stoller

Michel S Michail

George E Smith, Iii

Albert Y Chang

Gurumakonda R Srinivasan

John Balyoz

David B Eardley

Haluk O Askin

Peter Tsung-Shih Liu

Guy Rabbat

Alan K Chan

Emilio Colao

Ming T Cheng

Achilles A Sarris

Doyle E Beaty, Jr

A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; a sensing circuit connected to each of the base-collector terminals in the transistor pair, each of the sensing circuits including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) a circuit connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; a writing circuit connected to each of the transistors in the transistor pair, the writing circuit including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and a circuit for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.

High speed memory cell with multiple port capability

A current switch emitter-follower logic circuit allows both the UP output logic level and the DOWN output logic level to be independently controlled with respect to a fixed reference voltage so as to permit very small output level swings. A feedback circuit generates two different control signals which are independently variable and are input to a control circuit and to a logic circuit to compensate for fluctuations in power supply voltages, temperature and circuit parameters. These control signals are applied to a variable current source within the logic circuit and to a dynamic resistance within the control circuit to compensate almost instantaneously to fluctuations in power supply voltage, temperature or circuit device parameters, maintaining the logic circuit output levels close to reference levels so as to permit small output signal swings. The output logic levels need not be symmetrical around a central reference point.

Current switch logic circuit with controlled output signal levels

A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of polysilicon material, are then formed on the surface of the substrate. The connectors have bonding pad areas located along predetermined lines where metal connectors of later-formed metallization layers can be located. Some of the connectors have bonding pad areas connected to circuit elements while others are left unconnected. The subsequently formed metallization layers can then be used to connect together various ones of the circuit elements and multiple ones of the cells together in any desired circuit configuration using the polysilicon connectors.

VLSI integrated circuit having parallel bonding areas

A logic circuit network with circuitry for independently controlling at least one of the logic levels generated thereby, comprising, in one embodiment, a logic circuit with an output current node, a complement output current node, and at least one input line, the circuit for generating an output voltage level at the output current node which depends on the amount of current drawn therethrough, and for generating a complement output voltage level at the complement output current node which depends on the amount of current drawn therethrough; in combination with a current drawing means for drawing a controlled amount of current through one of those nodes to adjust the voltage level at that node. In one embodiment, this current drawing means is connected to a voltage reference level V.sub.R1, and operates to draw an amount of current from whichever current node is at a voltage level which is closest to a predetermined constant plus this voltage reference level V.sub.R1. The amount of current drawn is controlled to cause this closest node voltage level to approach this predetermined constant plus V.sub.R1. In a preferred embodiment this current drawing means comprises a separate differential amplifier connected to each of the output current nodes.

Logic level control for current switch emitter follower logic

A simultaneous bi-directional transceiver is described. The transceiver comprises two circuits which are disposed at opposite ends of an interchip cable. In response to the application of digital data signals to these circuits, they generate a trilevel voltage at the ends of the interchip cable. Then, in each circuit, a first input to a differential amplifier is generated from the trilevel voltage by a level shifter comprising a first diode and a first constant current sink and a second input to the differential amplifier is derived from the digital data input signal applied to that circuit by a level shifter comprising a second diode and a second constant current source. Finally, the transceiver outputs are generated from the differential amplifier outputs.

Bi-directional transceiver circuit

A network composed of a plurality of compensated current switch emitter-follower logic circuits and a generator of a current source control potential for the current sources of the logic circuits in which a symmetrical relationship between UP and DOWN logic levels is maintained at all times. A logic level tracking signal which tracks changes in the UP and DOWN logic levels in the logic circuits is produced by simulating at least a portion of one of the logic circuits. The logic level tracking signal is compared with the reference potential used for the logic levels, preferably ground, by a differential amplifier. The output of the differential amplifier is buffered and suitably level shifted to produce the current source control potential. The current source control potential is applied from the single control potential generator to each of the logic circuits. The control potential is also applied to the control input of a current source portion of the simulating circuit.

Reference-regulated compensated current switch emitter-follower circuit

Structure of an improved bipolar transistor

This dynamic reference potential generating circuit arrangement is especially adaptable to a binary data storage array of the type wherein each data storage cell comprises a single transistor and a single capacitor. A reference potential generating circuit for such an array comprises a pair of such identical transistors connected in parallel and a pair of identical capacitors, connected in common to the transistor emitter electrodes which capacitors couple the emitters to a digit line and to a refresh line, respectively. This arrangement develops a potential swing at the emitter electrodes equal to half of the potential swing that would develop at the emitter electrode of the transistor of a single data storage cell for the same signal swing on the digit line. Basically, the total capacitance connected to the emitter electrode of the generator circuit transistors is twice the capacitance connected to the emitter electrode of the transistor of a single storage cell. Therefore, the potential applied through the capacitor to the emitter electrode is exactly half of that applied through the capacitor connected to the storage cell transistor emitter electrode.

Dynamic reference potential generating circuit arrangement

An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

Process for fabricating a bipolar transistor

A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.

Unity gain emitter follower bridge circuit

A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the V.sub.be necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

Complementary transistor inverting emitter follower circuit

A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.

Selective epitaxy method for making filamentary pedestal transistor

A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.

Delay circuits using negative resistance CMOS circuits

An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is 'embedded' in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

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Hopewell Junction, NY, United States of America

Joseph R Cavaliere