Intel Corporation

Joseph R Bond

Herve R Lambert

Privavadan R Patel

An integrated circuit microcontroller with improved system bus timing modes that allow higher speed operation when accessing external memory. The improved system bus timing modes are generated by using the edges of a higher frequency secondary clock to trigger system bus timing events instead of using the edges of the phase clock. This can be done without major redesign using combinational logic because the phase clock and the higher frequency secondary clock are substantially in-phase.

Microcontroller having selectable bus timing modes based on primary and

A circuit for generating a square-wave output signal that is a frequency multiple of and substantially in phase with a reference input signal is described. The invention provides a phase-locked loop frequency multiplier circuit with a square-wave output signal that is substantially in phase with the reference input signal.

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San Jose, CA, United States of America

Joseph R Bond