Sun Microsystems, Inc.

Joseph Petollno

Renukanthan Raman

Samir Mitra

A cache memory controller and an associated method for fetching data are utilized to reduce the idle time of a central processing unit (CPU) of a computer system. Control circuitry and a plurality of cache fill status registers are provided to a cache controller to enable a data word to be fetched and returned to the CPU while a cache memory fill initiated due to a prior cache miss is still in progress. The data word is returned if the data word is stored in a main memory location which corresponds to a memory block offset of a main memory block frame currently being mapped into the cache memory. The data word is retrieved and returned to the CPU simultaneous with its writing into the cache memory, if the data word has not been written into the cache memory; otherwise, the data word is retrieved and returned to the CPU at the next dead cycle. As a result, CPU idle time due to cache read misses is reduced.

Growing community of inventors

Palo Alto, CA, United States of America

Joseph Petollno