Advanced Micro Devices Corporation

Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Joseph Patrick Geisler

Kin Hooi Dia

Michael J Allen

Chia-Wei Wang

Michael L Longwell

James Dennis Dodrill

Joern Soerensen

Norman Bujanos

Paul William Hollis

Matthew B Rutledge

Dimitry Patent

Lars Soendergaard Bertelsen

A pulse latch includes a pulse generator and a latch circuit. The pulse generator generates first and second pulse signals. The first pulse signal is generated when a test enable signal is in a first state, and the second pulse signal is generated when the test enable signal is in a second state. The latch circuit outputs the latched signal by selectively latching a normal data input signal or a test data input signal. The latch circuit includes first and second tri-state elements. The first tri-state element is controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state. The second tri-state element is controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state.

Pulse latches

A scan test circuit includes: a functional path, including: a D-type latch, for receiving an input and generating an output, the D-type latch including a feedback node; and a test path, including: a scan latch, for receiving a test input and generating an output. The scan test circuit also includes a tri-state inverter. The output of the test path is input to the feedback node of the D-type latch and also input to the tri-state inverter. The functional path is clocked by pulses generated by a pulse generator according to a system clock. The test path is clocked by a test clock generated according to a test enable signal and the system clock. When the test enable signal is enabled, the generation of the pulses is disabled.

Scan test circuit with scan clock

A dual power rail word line driver for driving a word line of a memory array according to a predecode signal from a decoder powered by a first supply voltage is provided. A signal buffering unit is coupled between the word line and a node. A pull-down unit is coupled between the node and a ground. A pull-up unit is coupled between the node and a second supply voltage higher than or equal to the first supply voltage. The signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the pull-down unit is turned on by the predecode signal and a first pulse signal and the pull-up unit is turned off by a second pulse signal. There is no level shifter on a critical timing path of the dual power rail word line driver.

Dual power rail word line driver and dual power rail word line driver array

An integrated circuit comprising a plurality of processing cores, characterised by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered.

Method of and apparatus for reducing power consumption within an integrated circuit

A bus control interface selectively and transparently couples a bus agent to a cache and to a memory to provide transparent burst access to addressable data having a portion residing in cache and a portion residing in memory. The bus control interface steers transactions to the cache or to the memory depending on where the data resides. In this way, the bus control interface supports, without a disconnect, burst read transactions that cross cache line boundaries. The bus control interface also supports bus watching single-word read (and write) transactions as well as burst write transactions.

Transparent burst access to data having a portion residing in cache and

An apparatus and method is provided for precharging a conductor within a bus containing a plurality of conductors. The apparatus comprises a precharge circuit which drives an intermediate voltage between VDD and ground upon respective conductors. The precharge driver maintains the intermediate voltage within a range between a first voltage level and a second voltage level, the second voltage level being higher in magnitude than the first voltage level. The precharge voltage defined within an intermediate voltage range is chosen to consume minimal power within the precharge driver. An isolation device can be provided on each conductor for isolating the intermediate, precharged value from a receiver circuit input so as to minimize power consumption of the overall circuit. Precharging to an intermediate value causes logic-driven transitions within the bus to occur at a faster frequency than if the bus were precharged to full rail. Intermediate precharge also minimizes noise crosstalk from transitioning neighboring conductors to a target conductor which is desired not to transition, and wherein the target conductor is interposed between the neighboring conductors.

Apparatus and method for precharging a bus to an intermediate level

A driver circuit is provided which unconditionally discharges a bus conductor during clock cycles in which the driver circuit is transmitting a value. The unconditional discharge occurs during a first drive phase of the logic drive state. During a second drive phase, the driver circuit either charges or continues to discharge the conductor based on the data value being transmitted. Since the conductors are transitioning in the same direction at approximately the same rate, line to line coupling is virtually non-existent during the first drive phase. By partially discharging bus conductors during the first drive phase, transition speed is increased to the point at which a receiving circuit senses the transmitted value. Effectively, the line-to-line coupling which would have occurred during the first drive phase is endured during the second drive phase, when certain conductors may be recharged. Shifting the coupling to the second drive phase results in the more rapid transition of the bus signals during the first drive phase.

Bus driver circuit configured to partially discharge a bus conductor to

An apparatus is provided for precharging a conductor within a bus containing a plurality of conductors. The apparatus comprises a precharge driver which precharges alternating pairs of conductors to opposite rail voltages. By precharging pairs of conductors to alternating rails, the present apparatus can minimize the speed degradation problems associated with a transitioning target conductor within the bus. Precharging alternating pairs of conductors also minimizes crosstalk noise from transitioning neighbor conductors to a non-transitioning target conductor. The improved dynamic bus thereby demonstrates improvements in speed degradation and crosstalk noise as seen by a transitioning target conductor or non-transitioning target conductor, respectively.

Growing community of inventors

Austin, TX, United States of America

Joseph Patrick Geisler