Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Other

Compaq Computer Corporartion

Joseph P Miller

Siamak Tavallaei

Paul R Culley

Sompong Paul Olarig

Alan L Goodrum

Mark E Taylor

Louis R Gagliardi

Donald J Stoddard

Randy M Bonella

Jeffrey S Autor

Jens K Ramsey

Chi Kim Sides

Mitchel E Wright

Michael C Sanders

B Tod Cox

John E Meyer

James H Singer

Roy E Thoma, Iii

Daniel Stuart Hull

Elizabeth A Richard

Robert R Covington

Eric E Rose

Karthigan Srinivasan

D Joseph Stoddard

Mark A Wade

Barry P Basile

Mike E Tullis

Craig A Borup

Bill Skelton

M Damian Cook

The use of operational configuration parameters to predict digital system failures is described herein. At least some illustrative embodiments include a method that includes initializing a digital system (the initializing comprising determining an operational configuration of at least part of the digital system), saving the operational configuration to a database stored on the digital system, reading the operational configuration from the database and comparing the operational configuration to a reference configuration, and identifying the digital system as being at risk of a future failure if at least one parameter of the operational configuration differs from the at least one same parameter of the reference configuration by more than a tolerance value.

Use of operational configuration parameters to predict system failures

A method and apparatus of testing a computer having a controller includes adjusting a reference voltage signal from a first level to a second level in response to an output from the controller. The first level is a level of the reference voltage signal during normal operation of the computer. Operation of a receiver in the computer is tested with the reference voltage signal set at the second level. An input of the receiver is connected to the reference voltage signal. Next, the reference voltage signal is adjusted back from the second level to the first level to enable normal operation of the computer.

Testing a receiver connected to a reference voltage signal

A system comprises a bridge, a slot coupled to the bridge, and a power control unit coupled to the slot via a common power rail and coupled to the bridge. An add-in card having one of a plurality of types can be installed in the slot. Upon installing the add-in card, the bridge determines the type of add-in card and asserts a logic signal to the power control unit. Based on the logic signal, the power control unit provides one of a plurality of direct current ('DC') voltages on the common power rail to the slot.

Power control unit that provides one of a plurality of voltages on a common power rail

In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Integrated circuit device/circuit board connection apparatus

A multi-pin edge connector assembly for connecting a daughter board to a mother board, for example, comprises a plurality of vias with conductive surfaces that are formed in the daughter board adjacent a connection edge. A plurality of openings are also formed in the daughter board, with each opening extending from the connection edge to one of the vias. Electrically conductive pins are positioned in the openings, with each pin having a first end in electrical contact with one of the conductive surfaces and a second end that projects beyond the connection edge for electrically contacting conductive pads or surfaces on the mother board. A retainer is mounted to the daughter board for holding the pins in their respective openings.

Multi-pin edge connector for circuit board

Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).

Delivering multiple optical signals using light that does not carry the data

A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

PCI hot spare capability for failed components

A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The video controller is further used for transmitting screen images to a remote computer system to facilitate system failure analysis. A plurality of system management remote units are provided for coupling to various components and busses within the host computer system. The system management remote units (SMR's) connect to the SMM via serial bus and permit the SMM to automatically monitor activities and operating conditions, including determining the source of interrupts on busses and detecting error conditions.

Computer diagnostic board that provides system monitoring and permits

A device causing a faulty condition in a computer system having devices is isolated by detecting for a faulty condition associated with the devices and identifying the device causing the faulty condition. The devices are coupled to a bus. The faulty condition includes a bus hang condition. The devices are turned off when a bus hang condition is detected. The devices are then turned back on to test the devices. Each device is tested by writing and reading its configuration space. Information on the bus associated with the faulty condition is stored. The stored information is retrieved after the faulty condition has occurred, with the stored information including address, data, and bus control information.

Method and apparatus for identifying faulty devices in a computer system

Data errors on a communications channel in a computer system are corrected. The data is transmitted over the communications channel in a sequence of time-multiplexed phases. A storage device accumulates the phases of data. An error detector and correction device checks the accumulated data for a data error and corrects the data error. The error detection and correction device can correct a one-bit data error, a two-bit data error, and a three-bit data error. Multiple bit errors can be corrected if the multiple bits of data are transmitted over one cable wire in multiple time phases. The communications channel carries the data over N sub-channels, and a parity check generator employs a predetermined parity check matrix based upon the N sub-channels and a probability that multiple errors in the accumulated data are attributable to a faulty sub-channel that affects the same data position in different time phases of the data. The error detection and correction device is operated based upon the parity check matrix. The communications channel includes a cable having N wire pairs, and the N sub-channels include the N wire pairs.

Data error detection and correction

Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

Method and apparatus for diagnosing fault states in a computer system

A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot of a computer system hot-pluggable, wherein a logic gate controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card whereas the other node is coupled to a bus to which the expansion slot is connected. The apparatus operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card from the bus when the system is running or during the powering up of the card.

Bus ring-back and voltage over-shoot reduction techniques coupled with

A technique for reducing skew between clock signals in a digital system requiring multiple clock signals. The system preferably is implemented on a printed circuit board. An oscillator circuit provides a periodic signal to a clock buffer which generates multiple periodic clock signals. The clock signals are provided to various destination points on the printed circuit board. The rising and falling edges of each clock signal generated by the clock buffer do not occur precisely at the same time as the rising and falling edges of the other clock signals. This misalignment of clock edges, or skew, is detrimental to system performance, but is reduced substantially by connecting all of the clock buffer's output clock signals together at a single physical point or node. Accordingly, the printed circuit board traces carrying each of the clock signals are routed to a single point node. A single point node is used to reduce skew caused by the clock buffer. Single point nodes also may be used at various locations on the printed circuit board to reduce skew caused by differences in the lengths of the traces carrying the clock signals.

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Cypress, TX, United States of America

Joseph P Miller