Motorola Corporation

Joseph P Gergen

Charles D Thompson

Kin K Chau-Lee

Bradley Martin

Garth D Hillman

Peter A Percosan

A multibit shifting apparatus (50) of a data processor (40) includes a multiplier (55) such as a modified Booth's recoded multiplier for use in normal multiplication operations. The multibit shifting apparatus (50) also uses the multiplier (55) to perform programmable left and right shifts in order to save circuit area. During a shift operation, a remapping circuit (54) receives a shift count, and remaps the shift count according to a shift direction to provide a remapped signal. The multiplier (55) receives both a shift operand and the remapped signal at inputs thereof. The multiplier (55) provides a first shift result at its output. In one embodiment, an output shifter (57) shifts the first shift result by a fixed amount selectively according to the shift direction to provide a second shift result. The second shift result includes outputs of both left and right shifts in common bit positions.

Multibit shifting apparatus, data processor using same, and method

A data processing system (10) which primarily supports fractional multiplication operations has a multiplication logic circuit (20) for executing integer multiplication functions efficiently. During an integer multiplication function, two multiplicands are multiplied together as if the multiplication function was fractional. A predetermined accumulation input is stored and shifted to the right by a Right Shift Logic circuit (32) before being added to a product of the two multiplicands. An accumulated product of the multiplication function is formed by an adder (36) and shifted to the left by a Left Shift Logic circuit (38) until the accumulated product is in integer form. Implementing an integer multiplication operation with a fractional multiplier in the data processing system requires a single software instruction.

Data processor with an integer multiplication function on a fractional

A data processor (10) having an instruction fetch unit (12), a decode and control unit (14), and an execution unit 16 performs conditionally executed instructions in hardware. A conditional break instruction, BRKcc, is inserted within a looping instruction to conditionally terminate the looping instruction with a minimum number of instruction cycles. A conditional do-loop instruction, DO#0, prevents the data processor (10) from executing a do-loop with a loop count within a loop counter (24) of zero upon entry. A conditional repeat instruction, REP#0, prevents a repeat instruction from being executed if a loop count is zero upon entry. A conditional repeat instruction, REPcc, allows a subsequent instruction to be conditionally terminated during execution.

Pipelined data processor which conditionally executes a predetermined

A technique for accomplishing a read, modify and write operation of a memory in a processor in a single cycle of the processor, where a cycle is understood as the time between successive loads of operands to the processor. A memory having two distinct portions of operands is provided wherein the single cycle operations are accomplished by virtually addressing the operands in a serpentine or snake-like configuration. A decoder is provided for efficiently controlling the concurrent reading and writing of operands and controlling the addressing of the memory.

Addressing technique for providing read, modify and write operations in

A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.

Cascade filter structure with time overlapped partial addition

A structure for implementing a plurality of independent filters, such as finite impulse response filters, in an efficient manner. Coefficient and data operands associated with each of the independent filters are stored in a predetermined order in a storage device and selectively coupled to an arithmetic unit for processing in a predetermined manner. Calculations for each filter are successively made and selectively stored. Although independent filters exist, processing circuitry is multiplexed and shared to substantially minimize associated control circuitry.

Growing community of inventors

Austin, TX, United States of America

Joseph P Gergen