Northern Telecom Limited

Joseph P Ellul

John M Boyd

Sing P Tay

Alexander Kalnitsky

Albert R Boothroyd

Michael B Rowlandson

Hak-Yam Tsoi

Jacques G Poirier

An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Integrated circuit structure and method of fabrication thereof

A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Method for forming integrated circuit structure

A buried layer contact for a integrated circuit structure is provided, with particular application for a contact for a buried collector of a bipolar transistor. The buried layer contact takes the form of a sinker comprising a fully recessed trench isolated structure having dielectric lined sidewalls and filled with conductive material, e.g. doped polysilicon which contacts the buried layer. The trench isolated contact is more compact than a conventional diffused sinker structure, and thus beneficially allows for reduced transistor area. Advantageously, a reduced area sinker reduces the parasitic capacitance and power dissipation. In a practical implementation, the structure provides for an annular collector contact structure to reduce collector resistance.

Buried layer contact for an integrated circuit structure

A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure. The resulting structure is fully planarized, preferably by chemical mechanical polishing, to form coplanar contact areas to the base and emitter.

Method of forming a transistor

A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension. The narrow portion of the trench is filled by the first conductive layer and after planarization provides an area of sufficiently large dimension for forming a contact to the first electrode. Contact to the second electrode is made in the first portion of the trench. Thus multiple electrodes for a trench capacitor are defined by a maskless process.

Trench capacitor structure

A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

Method of making integrated circuits

A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dependent on the trench width. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes.

Trench resistors for integrated circuits

Forming resistors for intergrated circuits

A low temperature CVD method is provided for depositing high quality stoichiometric, poly-crystalline silicon carbide films and for depositing emitter quality, heavily doped silicon carbide films, suitable for application in silicon hetero-junction bipolar transistors. The process is compatible with bipolar-CMOS device processing and comprises pyrolysis of di-tert-butyl silane in an oxygen free ambient, with n-type doping provided by phosphorus source comprising tert-butyl phosphine. Advantageously oxygen is excluded from the reactant gas mixture and the method includes pre-cleaning the susbtrate with nitrogen trifluoride and passivating the silicon carbide film with fluorine species from nitrogen trifluoride.

Method of forming silicon carbide

Method of forming electrodes for trench capacitors

An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.

Optical waveguide and method for its manufacture

In a method and apparatus for plasma stripping a polymer photoresist coating from a semiconductor substrate, positively charged species are removed from an activated gas flow before the gas flow is brought into contact with the coating to strip the coating from the substrate. The positively charged species may be removed by bringing the activated gas into contact with a grounded conducting surface to discharge the positively charged species, or by passing the activated gas through a negatively charged electrostatic filter to filter out positively charged species. The removal of positively charged species from the gas flow reduces or eliminates build up of positive charge on an outer surface of the photoresist coating so as to avoid driving mobile positively charged ions from the photoresist into the substrate, thereby avoiding contamination of the substrate.

Method and apparatus for removing coating from substrate

In a method and apparatus for plasma stripping a polymer photoresist coating from a semiconductor substrate, ultraviolet radiation generated as a byproduct of plasma generation is absorbed by a baffle placed between a plasma source and the substrate. The baffle inhibits incidence of ultraviolet light on the substrate while permitting flow of activated gas onto the substrate to chemically strip the photoresist from the substrate. Use of the baffle reduces microscopic damage to the substrate.

An integrated circuit device has a high resistivity silicon substrate in which a low resistivity region exists. A charge coupled array is fabricated in the high resistivity region and an output circuit is fabricated in the low resistivity region. At the boundary between the high and low resistivity regions a floating diffusion provides charge coupling between the array and the circuit. The low resistivity region is prepared in a high resistivity substrate at a temperature in excess of 1000.degree. C. to obtain a sufficiently deep low resistivity region but subsequent processing to produce the charge coupled array and the control circuit is performed at lower temperatures to minimize thermal degradation and contamination of the high resistivity region.

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Nepean, Canada

Joseph P Ellul