Digital Equipment Corporation

Sun Microsystems, Inc.

Joseph P Coyle

William B Gist, Iii

Garry Michael Tobin

Peter Nixon

Bus testing logic is built into some of the devices connected to the bus to enable these devices to perform diagnostic testing of the bus. Under control of the test logic, the devices drive the bus with output voltages corresponding to a predetermined test bit pattern that is selected to cause the bus to reach a target bus utilization level. The bus signals produced by the devices propagate along the bus and are received by other devices. The received bus signals are resolved into a received bit pattern. The received bit pattern is compared with the test bit pattern used to generate the bus signals in order to detect discrepancies. In one embodiment, the devices can operate in a first mode by driving the bus in accordance with performing normal functions or in a second mode by performing diagnostic testing on the bus by driving the bus in accordance with the test bit pattern. Test patterns can be interleaved with normal bus signals. Alternatively, the test logic in the devices can arbitrate with the normal circuitry to assume control of the bus for testing purposes. In still another embodiment, a first device includes both a bus driver and a bus receiver and a second device includes logic for looping the bus signals back to the device that generated the signals.

Method and apparatus for inducing bus saturation during operational testing of busses using a pattern generator

A test system for testing communications over a bus connecting electronic devices, e.g., components of a computer system is preferably embedded in the devices themselves rather than in apparatus external to them, and is responsive to digital control signals, e.g., conforming to JTAG, for scanning test data into and out of the devices. The test system has a stress injection module for injecting a set of stimulus patterns on the bus; an error identification module for identifying an error resulting from the set of stimulus patterns; a bus tuning module for adjusting one or more bus operating and signaling parameters so that testing can be performed at one or more of a number of different sets of operating and signaling parameters; a programmable control module for controlling the bus tuning module; and a presentation module for presenting a plurality of results of the testing.

Method and apparatus for operational envelope testing of busses to identify halt limits

A system for programmatically adjusting electrical characteristics of a bus interface so as to modify bus operating and signaling parameters employs a control module or mechanism, responsive to a digital signal, for setting the characteristic's value. The electrical characteristic can be a voltage determinative, for example, of any of the following bus operating and signaling parameters: driver output rise time, driver output fall time, driver voltage limits, driver propagation time, receiver threshold voltage levels, or termination resistance. The digital signal can be generated, for example, by a computer-executable program, a controller, or other such device, that applies the digital signal to the control mechanism, for example, via a JTAG interface/controller.

Method and apparatus for programmable adjustment of computer system bus parameters

A bus tuning system is provided for determining the configuration of an electronic device and for testing and tuning a bus system of the electronic device specifically for its configuration, the bus system including a bus interface coupled with a bus characterized by a number of parameters. The system has a mechanism for determining the configuration of the electronic device; a mechanism for injecting a set of stimulus patterns on the bus; a mechanism for collecting information regarding operation of the electronic device corresponding to the stimulus patterns, including information identifying any error resulting from the set of stimulus patterns; a mechanism for comparing the collected information with information corresponding to the configuration of the electronic device; a mechanism for determining, responsive to the comparing mechanism, whether the electronic device is operating within a predetermined set of operating specifications; and a mechanism for adjusting values of one or more of the parameters by varying one or more electronic characteristics of the bus interface in response to a set of digital control signals to obtain a set of operating and signaling parameters of the bus interface that cause the electronic device to operate within the predetermined set of specifications.

Method and apparatus for bus parameter optimization using probes of system configurations

Testing of an electronic system is optimized by using a single set of sub-tests and varying the testing sequence to produce tests tailored for different purposes such as screening and diagnostic testing. For example, a programmable test sequencer in the electronic system responds to a test selection variable by using a first sequence of the sub-tests to optimize the testing process for screening and a second sequence of the sub-tests to optimize the testing process for diagnostic testing. In the diagnostic mode, the sub-tests are run so that each sub-test builds upon the previous sub-tests and uses previously-tested hardware to verify additional hardware. In the screening mode, the sub-tests are the same, but the execution order of the sub-tests is reversed so that more complex hardware is tested first as a screening mechanism.

Method and apparatus for optimizing testing sequences for electronic equipment

Information regarding the operating conditions of a computer system is stored in a storage which is dedicated to a failure management system. The storage is updated with the current operating conditions either periodically or upon the occurrence of predetermined events. When a first failure identification mechanism identifies a failure in the computer system, a capture mechanism interrupts the updating of the storage leaving information regarding operating conditions which contributed to the failure in the storage. This latter information can then be read out to aid in diagnosis of the failure. Since the operating condition information is stored in a dedicated storage, the information is not modified by events that take place after the failure is identified. In accordance with one embodiment, the computer system ordinarily holds state and other operating information in a set of storage devices, such as, for example, state registers. The dedicated storage device can be a shadow register or other shadow storage device for holding a separate dedicated copy of at least a portion of the operating information so that it is readily available in case a failure is detected. During operation, an updating mechanism continually transfers the information in the state registers to the shadow register until a first failure is detected. When a failure is detected, a capture mechanism controls the updating mechanism to cease transferring information from the state registers to the shadow register. The shadow register can then output its contents, e.g., for analysis, preferably under computer program control.

Method and apparatus for extracting first failure and attendant operating information from computer system devices

A HASS testing system provides for testing and tuning of a bus system of an electronic device having a bus interface coupled with a bus characterized by a number of parameters. The HASS testing system includes a mechanism embedded in the device for injecting a set of stimulus patterns on the bus; a mechanism embedded in the device for collecting information regarding operation of the electronic device corresponding to the stimulus patterns, including information identifying any error resulting from the set of stimulus patterns; a mechanism for comparing the collected information with corresponding information collected during baseline testing; a mechanism for determining, from the comparing step, whether the device is operating within a predetermined set of operating specifications; and a mechanism embedded in the device for adjusting values of one or more of the parameters by varying one or more electronic characteristics of the bus interface in response to a set of digital control signals to obtain a set of operating and signaling parameters of the bus interface that is cause the device to operate within the predetermined set of specifications.

Method and apparatus for HASS testing of busses under programmable control

A bus driver introduces a propagation delay of programmable duration prior to transmission of data over a bus. The bus driver has an input stage for acquiring data for transmission over a bus and an output stage having a driver circuit for transmitting data received from the input stage over the bus. The input stage has a first storage element for storing the data for a first period of time responsive to a first clock signal; and a second storage element for storing the data received from the first storage element for a second period of time whose duration is responsive to a second clock signal. The bus driver also has a programmable delay module coupled with the second storage element for regulating the second clock signal in response to a programmable digital signal and thereby regulating duration of the second period of time. The digital signal can be generated, for example, by a computer-executable program, a controller, or other such device, that applies the digital signal, for example, via a JTAG interface/controller.

Method and apparatus for programmable adjustment of bus driver propagation times

An I/O bus into the cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Semiconductor process, power supply and temperature compensated system

An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination Circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Semiconductor process power supply voltage and temperature compensated

An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Reduced system bus receiver setup time by latching unamplified bus

Semiconductor process, power supply voltage and temperature compensated

Integrated I/O bus circuit protection for multiple-driven system bus

Externally programmable integrated bus terminator for optimizing system

An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

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Leominster, MA, United States of America

Joseph P Coyle