Apple Inc.

Silicon Graphics, Incorporated

Kabushiki Kaisha Toshiba

Mips Technologies, Inc.

Joseph P Bratt

Sushma Shrikant Trivedi

Guy Cote

Jack Benkual

Timothy John Millet

Peter F Holland

Jerome Francis Duluk, Jr

Richard E Hessel

Vaughn Todd Arnold

Simon Wolfenden Butler

Stephen L Dodgen

Matthew N Papakipos

Nathan D Tuck

Jason Rupert Redgrave

Suk Hwan Lim

D Amnon Silverstein

Emerson S Fang

Sidong Li

Shun Wai Go

Hengwei Hsu

George Cuan

Sam Ng

Zhaoyu Gong

Joseph Anthony Petolino, Jr

Thomas Y Ho

Shing Horng Choo

David Gerard Conroy

Jeffrey E Frederiksen

Peter Y Hsu

Steven David Hordley

Joseph T Scanlon

Tuan Anh Nguyen

Sheng Lin

William C Athas

William A Huffman

Graham D Finlayson

Abbas Rashid

Guy Côté

Weichun Ku

Derek Fujio Iwamoto

Joseph J Cheng

Abraham Mammen

Bo Hong

John Brennan

Joseph P Grass

Lindy Fung

Albert Suan-Wei Tsay

Brijesh Tripathi

Steven Todd Weybrew

Man K Tang

Jim Chen Chou

Manu Gulati

Mark Zimmer

Joshua P De Cesare

William P Cornelius

Hao Chen

Paul A Baker

Gurjeet S Saund

David Hayward

Conrad Sauerwald

Gokhan Avkarogullari

Rohit Kumar Gupta

Deniz Balkan

Jung Wook Cho

Paul Kingsley Rodman

Mark P Rygh

Ronald Ray Hochsprung

Craig M Okruhlica

Chandra Shekhar Joshi

Alexei V Ouzilevski

Weihua Mao

Nitin Bhargava

Kevin C Wong

David Ligon

Ronald Gerard Langhi

Monica R Nofal

Ron Hochsprung

Man Kit Tang

Steve J Ciavaglia

Lakshmi Rao

David L Bowman

Jason Chen

Yutaka Takahashi

Gaurav S Gulati

Shing I Kong

Peter Yan-Tek Hsu

Steve Ciavagia

John Brennen

Steven J Ciavaglia

Timothy J Millett

Thomas Y Yo

Chandra S Joshi

Joseph T Apartment K-209 Scanlon

Systems and methods for down-scaling are provided. In one example, a method for processing image data includes determining a plurality of output pixel locations using a position value stored by a position register, using the current position value to select a center input pixel from the image data and selecting an index value, selecting a set of input pixels adjacent to the center input pixel, selecting a set of filtering coefficients from a filter coefficient lookup table using the index value, filtering the set of source input pixels to apply a respective one of the set of filtering coefficients to each of the set of source input pixels to determine an output value for the current output pixel at the current position value, and correcting chromatic aberrations in the set of source input pixels.

Raw scaler with chromatic aberration correction

Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

Chroma cache architecture in block processing pipelines

Systems and methods for local tone mapping are provided. In one example, an electronic device includes an electronic display, an imaging device, and an image signal processor. The electronic display may display images of a first bit depth, and the imaging device may include an image sensor that obtains image data of a higher bit depth than the first bit depth. The image signal processor may process the image data, and may include local tone mapping logic that may apply a spatially varying local tone curve to a pixel of the image data to preserve local contrast when displayed on the display. The local tone mapping logic may smooth the local tone curve applied to the intensity difference between the pixel and another nearby pixel exceeds a threshold.

Systems and methods for local tone mapping

A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.

Clock control for DMA busses

Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline.

Data storage and access in block processing pipelines

Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Global configuration broadcast

A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

Buffer underrun handling

Systems and methods for processing image data in RGB format are provided. In one example, an electronic device includes memory to store image data in raw or RGB format, or both, and an RGB image processing pipeline to process the image data. Specifically, the RGB image processing pipeline may process the image data regardless of whether the image data is of raw or RGB format. The RGB image processing pipeline may include receiving logic to receive the image data in raw or RGB format and demosaicing logic to, when the receiving logic receives the image data in raw format, convert the image data into RGB format. The logic may include local tone mapping logic configured to apply spatially varying tone curves to the image data, a color correction matrix configured to correct color in the image data, and gamma logic configured to transform the image data into gamma space.

Systems and methods for RGB image processing

A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Parameter FIFO

Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Protocol conversion involving multiple virtual channels

Systems and methods for generating local image statistics are provided. In one example, an image signal processing system may include a statistics pipeline with image processing logic and local image statistics collection logic. The image processing logic may receive and process pixels of raw image data. The local image statistics collection logic may generate a local histogram associated with a luminance of the pixels of a first block of pixels of the raw image data or a thumbnail in which a pixel of the thumbnail represents a downscaled version of the luminance of the pixels of the first block of the pixel. The raw image data may include many other blocks of pixels of the same size as the first block of pixels.

Local image statistics collection

Growing community of inventors

San Jose, CA, United States of America

Joseph P Bratt