Rca Inc.

Rca Thomson Licensing Corp.

Joseph O Sinniger

Anthony D Robbi

James Henry Arbeiter

Roger Frank Bessler

Gooitzen Siemen Van Der Wal

Charles H Anderson

Richard M Peterson

First circuit apparatus, comprising a given number of prior-art image-pyramid stages, together with second circuit apparatus, comprising the same given number of novel motion-vector stages, perform cost-effective hierarchical motion analysis (HMA) in real time, with minimum system processing delay and/or employing minimum hardware structure. Specifically, the first and second circuit apparatus, in response to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-data frames that occur at a relatively high frame rate (e.g., 30 frames per second), derives, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between each pair of successive image frames.

Implementation architecture for performing hierarchical motion analysis

The amount of hardware required to implement a Burt Pyramid or an FSD (filter-subtract-decimate) pyramid analyzer (or synthesizer) stage of a sampled temporal signal representing an n-dimensional information component or (such as a video signal) is substantially reduced by employing a time-synchronized multiplexed analyzer stage to derive (or a time-synchronized multiplexed synthesizer stage that is responsive to) a single serial stream of samples of a predetermined plural number of sub-spectra that are arranged in a predetermined temporal order format with respect to one another in accordance with each of a given set of time synchronized, repetitively generated, serially applied control signals.

Multiplexed real-time pyramid signal processing system

A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Digital timing system

Digital timing method for spark advance

A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.

Multiplex bus system for controlling the transmission of data between a

A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter. Improved memory addressing means facilitates altering the spark advance in accordance with a sensed condition such as manifold vacuum, and conserves memory space.

Digital timing system for spark advance

A digitized duty cycle pulse generator capable of resolution finer than the period of the available source clock signal. The invention comprises a means for generating a clock pulse signal having a repetition of f.sub.c, counter means responsive to said clock pulse signal to cycle iteratively through a count of n, and storage means for storing a variable binary value m, where m&lt;n and m is the length of the desired duty cycle pulse, and where m/n is the duty cycle. Also provided are logic means comprising comparator means responsive to the instantaneous count l in said counter means and the value m in said storage means when m is not an integer to produce a first logic level signal when l&lt;m and a second logic level signal when l&gt;m during first selected cycles of said counter means through said count of n, and to produce said first logic level signal when l&lt;(m+1) and said second logic level signal when l&gt;(m+1) and during second selected cycles of said counter means through said count of n.

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Pennington, NJ, United States of America

Joseph O Sinniger