Texas Instruments Corporation

Joseph O Liu

Christopher Daniel Manack

Vivek Swaminathan Sridharan

Michael Todd Wyant

Genki Yano

Shoichi Iriguchi

Matthew John Sherbin

Hiroyuki Sada

Yuan Zhang

Jeniffer Otero Aspuria

Venkataramanan Kalyanaraman

Ming Zhu

Gelline Joyce Untalan Vargas

Qing Ran

Hao Zhang

Yang Liu

In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound, the conductive member exposed to an exterior surface of the mold compound.

Efficient removal of street test devices during wafer dicing

A method of dicing a wafer includes positioning the wafer with its top side on a tape material. The wafer includes a plurality of die separated by scribe streets. A first pass being a first infrared (IR) laser beam is directed at the bottom side with a point of entry within the scribe streets. The first IR laser beam is focused with a focus point embedded within a thickness of the wafer, and has parameters selected to form an embedded crack line within the wafer. The embedded crack line does not reach the top side surface. A second pass being a second IR laser beam is directed at the bottom side having parameters selected to form a second crack line that that has a spacing relative to the embedded crack line, and the second IR laser beam causes the embedded crack line to be extended to the top side surface.

Splash resistant laser wafer singulation by crack length control

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

Efficient redistribution layer topology

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

Semicondutor package substrate with die cavity and redistribution layer

A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.

Front side laser-based wafer dicing

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Dallas, TX, United States of America

Joseph O Liu