Intel Corporation

Joseph Nuzman

Ron Gabor

Tomer Stark

Raanan Sade

Jason W Brandt

Gilbert A Neiger

Rajesh M Sankaran

Robert S Chappell

Igor Yanover

Niall D McDonnell

Koichi Yamada

Stephen R Van Doren

Ady Tal

Robert Valentine

Mark Jay Charney

Yen-Cheng Liu

Larisa Novakovsky

Jeffrey J Cook

Jesus Corbal

Edward Thomas Grochowski

Eriko Nurvitadhi

Thomas D Fletcher

Deborah T Marr

Dennis Ryan Bradford

Paul Caprioli

Lokpraveen B Mosur

Narayan Ranganathan

Kent D Glossop

Deepak K Gupta

Jonathan D Pearce

Richard J Greco

Ganesh Venkatesh

Jared Warner Stark, Iv

Asit K Mishra

Stephen J Robinson

Dwight P Manley

Tracy Garrett Drysdale

David B Sheffield

Nicholas P Carter

Liron Zur

Vedvyas Shanbhogue

David A Koufaty

Bryant E Bigbee

Lihu Rappoport

Shlomo Raikin

Ahmad Yasin

Samantika S Sury

Leeor Peled

Ravi L Sahita

Christopher J Hughes

Youfeng Wu

Raj K Ramanujan

David J Sager

Alexander Gendler

Stanislav Shwartsman

Asit K Mallick

Sergiu D Ghetie

Rodrigo Branco

Tin-Fook Ngai

Ruchira Sasanka

Doddaballapur N Jayasimha

Mingwei Zhang

Scott P Bobholz

Suresh Srinivas

Subramanya R Dulloor

Jonas Svennebring

Jayaram Bobba

Ho-Seop Kim

Omar M Shaikh

Wojciech S Powiertowski

Sagar V Dalvi

Mohan J Kumar

Glenn J Hinton

Tsung-Yuan Charles Tai

Amit Gradstein

Ren Wang

Carlos V Rozas

Baiju V Patel

Andrew V Anderson

Richard A Uhlig

Andrew J Herdrich

Anil Vasudevan

Sanjay Kumar

Xiang Chris Zou

Kai Cheng

Ishwar Agarwal

Alaa R Alameldeen

Sailesh Kottapalli

Bahaa Fahim

Abhishek Basak

Leena K Puthiyedath

Rahul Pal

Namakkal N Venkatesan

Hisham Shafi

Rinat Rappoport

Vivekananthan Sanjeepan

Francis McKeen

Ashok Jagannathan

Ayan Mandal

Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

Apparatuses, methods, and systems toprecisely monitor memory store accesses

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.

Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bit

An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

Dynamic inclusive last level cache

In one embodiment, a processor includes: one or more execution circuits to execute instructions; a stream prediction circuit coupled to the one or more execution circuits, the stream prediction circuit to receive demand requests for information and, based at least in part on the demand requests, generate a page prefetch hint for a first page; and a prefetcher circuit to generate first prefetch requests each for a cache line, the stream prediction circuit decoupled from the prefetcher circuit. Other embodiments are described and claimed.

System, apparatus and method for prefetching physical pages in a processor

Apparatuses, methods, and systems to precisely monitor memory store accesses

An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

Memory tagging apparatus and method

Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

Restricted speculative execution mode to prevent observable side effects

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

Hardware apparatuses and methods for memory corruption detection

Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

Apparatuses, methods, and systems for instructions to compartmentalize code

Growing community of inventors

Haifa, Israel

Joseph Nuzman