Intel Corporation

Other

Tela Innovations, Inc.

Joseph N Hong

Scott T Becker

Rabiul Islam

Michael C Smayling

Stephen Kornachuk

Brian Reed

Lloyd Briggs

Stephen Fairbanks

Subodh Annojvala

Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

Methods for defining and utilizing sub-resolution features in linear topology

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

Methods for defining contact grid in dynamic array architecture

Bitcell layouts for use in electronic devices and systems are described. One embodiment relates to a memory including at least one bitcell, the bitcell including a storage cell region and a read channel region. The storage cell region is substantially L-shaped and includes six transistors. The read channel region is shaped to fit together with the substantially L-shaped storage cell region to form a substantially rectangular bitcell shape. Other embodiments are described and claimed.

Bitcell layout

A storage cell having a storage circuit and a readout circuit may be used in power-saving environments, where the storage circuit may be maintained in an ultra-drowsy mode during power-saving periods while the readout circuit may be powered down during power-saving periods. A pull-down transistor may be incorporated into the readout circuit to reduce current leakage during power-saving periods.

State-retentive mixed register file array

Cache memory systems, microprocessors, and computer systems, as well as methods of operating a cache memory system are described. The cache memory system includes a cache memory controller coupled to a dynamic cache memory and a static cache memory. The cache memory system provides the advantages of using dynamic memory (having a small circuit real estate requirement) for cache read operations, and static memory for cache write operations. Using the static memory for cache write operations allows the cache memory system to function as a write-back cache, instead of an instruction-only, or write-through cache.

Memory management apparatus and method

A domino-logic latch device may include a domino-logic block formed, e.g., of a transistor and a static inverter, a precharge transistor configured to precharge a sensing node to a precharge logic level, a logic block arranged between the sensing node and an intermediate node, and configured to receive one or more input signals to be evaluated during a predetermined interval, a latching transistor, arranged between the sensing node and the intermediate node and configured to latch an evaluated logic level of the logic block during the predetermined interval, and a discharge transistor, coupled to the intermediate node, configured to conditionally discharge the sensing node to a discharge logic level based on the input signals evaluated by the logic block.

Latch circuit

A main body portion of a shoe includes a base having a heel and a sole, and an upper on the base. A lower sole is positioned below the base sole and is movable front to rear and back relative to the base sole. A transducer is provided in the seal and is connected to the lower sole. The transducer pushes the lower sole forwardly in response to heel pressure being imposed by the heel of the wearer on the heel of the shoe. After a forward shoe is set down on the ground, with its heel up and its lower sole contacting the ground, the main body portion of the shoe, with the wearer's foot inside of it, slides forward and adds length to the step.

Step lengthening shoe

A golf club of the type for putting and driving a golf ball. The golf club has a reflective surface which is positionable to direct toward a golfer's eye an alignment image including an image of the ball and the target into which the ball is directed so as to aid the golfer in positioning the head of the golf club relative to the ball. The reflective surface is removable from the head so as to be stowed when not in use. The golf club also includes a leveling device in the head of the club to indicate to the golfer when the head is aligned horizontally. The golf club further includes a first striking surface with a tilted striking surface portion for imparting spin to the golf ball, and a second striking surface opposite the first for directing the ball in an upward trajectory. The tilted striking surface may include a flat central portion and an adjacent flat end portion, both of which contact the golf ball. Third and fourth striking surfaces are positioned between the first and second striking surfaces at opposite ends of the head. To strike the ball with the third or fourth striking surfaces, the golfer positions himself behind the ball and astride a desired path between the ball and the target.

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Cupertino, CA, United States of America

Joseph N Hong