3com Corporation

Hewlett-packard Development Company, L.p.

Joseph N Butler

Neil O Fanning

Eugene O'Neill

Mark A Hughes

Kevin Jennings

Sorcha O'Callaghan

Daniel M O'Keeffe

Kevin Loughran

Una Quinlan

A network switch includes a look-up engine for obtaining associated data in response to a header portion of a packet and an interlinked network processor such as a RISC for performing a processing function on the header portion or the associated data. Both look-up engine and the network processor may modify a destination port bitmask. The network processor may implement additional packet header processing required for replication or server load balancing.

Network switch with mutually coupled look-up engine and network processor

A method and switch for controlling the allocation of priority of TCP packets, more particularly for distinguishing between data and control packets and assigning an increased priority to control packets. The layer 4 information in the form of the flag bits of the header are snooped in the switch to determine whether any flag other than PSH is set and if so to allocate a priority to that packet, which will usually be a higher priority than data packets.

TCP control packet differential service

An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.

On-chip detection of clock gitches by examination of consecutive data

A high speed link between chips and comprising a multiplicity of synchronous serial data channels includes an onboard detector for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest error rate as the control channel and optionally to render at least the channel with the highest error rate inactive.

Growing community of inventors

Galway, Ireland

Joseph N Butler