International Business Machines Corporation

Joseph Michael Sullivan

Ajay Prabhakar Giri

Emanuele F Lopergolo

Lewis Sigmund Goldmann

Voya Rista Markovich

Sampath Purushothaman

Roy Rongqing Yu

Eric D Perfecto

Chandrika Prasad

Giulio DiGiacomo

Christopher Lee Tessler

Kimberley A Kelly

Bouwe W Leenstra

Arden Steuart Lake

Richard L Canull

Glenn Graham Daves

Charles R Tompkins, Jr

Peter M Elenius

Dennis Felix Clocher

Joseph John Lisowski

A method of forming a multichip module in which a thin film structure is formed on a temporary carrier and then an electrically insulating frame is attached to the thin film structure. A semiconductor device is attached to the thin film structure and then the temporary carrier is removed. Lastly, at least one semiconductor device is attached to the other side of the thin film structure. There is interconnectvity through the thin film structure between the semiconductor devices and the frame.

Method of forming a multichip module having chips on two sides

A multichip module including a frame having contacts suitable for making an electrical connection with an article, preferably a printed wiring board or similar, which is the next level of packaging, a multilayer thin film structure mounted to the frame, and semiconductor devices mounted to the thin film structure with at least one semiconductor device on each of two opposed sides of the thin film structure. The thin film structure includes arrays of pads on opposed surfaces of the thin film structure for connecting the thin film structure to the semiconductor devices and the frame. The thin film structure further includes wiring for chip to chip connectivity and for connecting to the frame.

Multichip module having chips on two sides

A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Process for forming a multi-level thin-film electronic packaging structure

A method, system and structure for a pin grid or pad grid array structure includes a plurality of pins connected to an electronic structure, a power plane within the electronic structure electrically connected to power pins, a ground plane within the electronic structure, and fuse portions electrically connecting the ground plane to ground pins and signal pins. The power plane and the ground plane create a charge in the pins during electroplating of the pins. The fuse portions disconnecting the signal pins from the ground plane after the electroplating.

Method for shorting pin grid array pins for plating

A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Multi-level thin-film electronic packaging structure and related method

A high performance, low cost multi-chip module package using a heatsink as a substrate with thin film wiring techniques or multilayered wiring techniques for interconnection of the chips on the surface of the module and a solder column grid array or solder ball grid array for interconnection to the next level of packaging (printed circuit board). The columns or balls create a space between the board and module with the chips being in the space and provide the required interconnect density.

High performance, low cost multi-chip modle package

The present invention relates generally to a new apparatus and method for use in chip, module, card, etc., burn-in and/or test or electrical interconnection. More particularly, the invention encompasses an apparatus that is used as a temporary media between a chip, module, card, etc., that needs to be tested and/or burned-in and a test or burn-in system. A method for such burn-in and/or test or electrical interconnection is also disclosed. The invention also encompasses an apparatus and a method that can be used as a permanent media between two electrical devices, such as, for example, between a chip and a module or a card, etc., that is to be contained in and part of a system.

High density electrical interconnect apparatus and method

A probe assembly comprising a frame and at least one contact carrier within the frame wherein the carrier has a plurality of tie strips and a plurality of contacts and each contact is contiguous with a corresponding group of tie strips. Each contact becomes discontiguous from the corresponding group of tie strips when a force is applied to the tie strips. The probe assembly further comprising at least two rails attached to the frame. Each rail has a top portion for receiving the contacts and tie strips and a bottom portion having a plurality of regions for contacting the tie strips. The carrier is positioned between the top portion of one of the rails and the bottom portion of the other rail. When a compressive force is applied to the rails and carrier, the regions forcibly contact the tie strips such that all the contacts simultaneously become discontiguous from the tie strips.

Growing community of inventors

Wappingers Falls, NY, United States of America

Joseph Michael Sullivan