International Business Machines Corporation

Joseph Michael Fitzgerald

Anthony Gus Aipperspach

Douglas Michael Dewanz

Dennis T Cox

Durations of activities in forming a system (the 'current system') are estimated, using data including i) durations of first activities and scores for a number of previously formed systems (the 'past systems'), ii) scores for the current system, and iii) a model defining a relationship between duration of the first activities and such scores. A factor for the model is computed in response to the first activities and scores for the past systems. An expected duration for first activities of the current system is computed in response to the computed factor and the scores for the current system. The scores for such systems are generated by defining and scoring subsystems for the system and combining the scores of the subsystems. Scoring further includes identifying risks having a potential impact on duration of the activities and assigning weights to the risks; identifying a number of possible conditions ('PC's') relating to the risks, associating degrees of the risks with the PC's, such as by ranking the PC's; defining a relation between an expected condition ('EC') and the PC's; and computing a score in response to the EC's, relations between EC's and PC's, the degrees of risks associated with the PC's, such as may be defined by the rank of the PC's and the weights of the risks.

Method and apparatus for estimating durations of activities in forming a

A circuit macro is provided for a VLSI circuit device having a semiconductor substrate and M1 and M2 metal layers defining a grid of M1 and M2 conductive lines extending in orthogonal directions. Numerous similar unit cells are arrayed side-by-side in rows extending in one direction and each unit cell spans an integral number of M1 conductive lines and an integral number of M2 conductive lines. The circuit device includes a plurality of circuit blocks each including two of the rows of unit cells. A plurality of wiring bays extend between adjacent circuit blocks, and each wiring bay includes a plurality of M1 conductive lines. The circuit macro includes a number of circuti blocks separated by wiring bays, and connections extend to unit cells of circuit blocks included in the macro. Both M1 and M2 conductive lines are used for connections in the macro, and additional M1 and M2 conductive lines, including M1 connductive lines in the wiring bays, extend uninterrupted across the macro providing a porous yet dense macro and facilitating macro placement and wiring.

Porous circuit macro for semiconductor integrated circuits

A macro generation method and a macro structural arrangement are provided for a VLSI semiconductor circuit device. A circuit macro is defined by a plurality of circuit blocks including at least one control block and an identified number of storage blocks. The control block includes a control section, a bit decoder section, a word decoder section and a work selector section. Each of the storage blocks includes a memory section, a bit selector section and a sense latch driver section. One of a plurality of stored predetermined bit decoders is selectively provided for the bit decoder section. A required number of storage blocks is identified responsive to the selected bit decoder for the selected number of bits per word. A required number of word selectors and memory array subsections is identified responsive to the selected bit decoder for the selected number of words.

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Austin, TX, United States of America

Joseph Michael Fitzgerald