Texas Instruments Corporation

Joseph Michael Erickson

Jin-Meng Ho

Alon Paycher

Brian T Deng

Yaser M Ibrahim

Dinghui Richard Nie

Horng-Ming Tai

One embodiment of the present invention includes a system for managing timing functions associating with at least one timing protocol. The system comprises a controller configured to implement a plurality of functions at each of a respective plurality of scheduled times. The system also comprises a time protocol converter configured to convert each of the plurality of scheduled times to a respective plurality of time values associated with a master timing protocol. The system further comprises a master timer controller configured to generate a plurality of control signals associated with the plurality of functions based on an accumulated value of a master timer associated with the master timing protocol relative to the plurality of time values.

Systems and methods for managing timing functions in multiple timing protocols

A retry algorithm determines the maximum number of transmissions and retransmissions that may be attempted for the frame in the head of a transmit queue or transmit buffer that needs to be transmitted across a communications link. The algorithm attempts to achieve a constant delay for each packet in frame by taking into account the number of frames residing in the transmit queue, the number of transmit opportunities elapsed between the arrivals of two successive frames in the transmit queue s, as well as the buffering capabilities of both the transmitting and receiving sides. The transmission and retransmission control technique provides for a way of managing the TX and RX buffers with a size that is suitable for the application being used and the underlying transport network. The number of retries is adapted to incoming and outgoing data rate changes in order to provide a fixed delay wireless link transport and maximize effective channel utilization.

Method and apparatus for providing retry control, buffer sizing and management

A bridge controller controls the data flow to/from a USB bus to/from an ATA/ATAPI drive, such as an ATA hard drive or ATAPI CD or DVD drive. The bridge controller has a state machine which receives the CBW in a background mode in real time as the packet is being transferred to the bridge controller. The state machine uses the CBW to set up the data transfer. The bridge controller also has a programmable processor which is coupled to the CBW once it is received in a buffer memory. The programmable processor makes changes in the set up of the receiving device for the transfer, if needed, and initiates the data transfer.

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Frisco, TX, United States of America

Joseph Michael Erickson