Texas Instruments Corporation

Unitrode Corporation

Joseph Maurice Khayat

Brian Thomas Lynch

Henry Litzmann Edwards

Marie Denison

Michael G Amaro

Robert Allan Neidorff

Stefan Wlodzimierz Wiktor

Bharath Balaji Kannan

Ashish Khandelwal

Ramanathan Ramani

Yipeng Su

Pradeep S Shenoy

Archana Venugopal

Robert Alan Neidorff

Stephen Isaac Brink

Jin-Biao Huang

Wei Da

Sergio Carlo-Rodriquez

Aditya Makharia

Marco Corsi

Osvaldo Jorge Lopez

Robert A Priegnitz

Fei Ma

Ubol Udompanyavit

Geoffrey Potter

Matthew Thomas Murdock

Jeffrey D Putsch

David R Olson

Timothy Goodrow

Lemuel Herbert Thompson

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

High voltage avalanche diode for active clamp drivers

A switching regulator includes a low-side switching transistor, a snubber transistor, a first pull-down transistor, and a second pull-down transistor. The low-side switching transistor includes a first current terminal and a second current terminal. The first current terminal is coupled to a switching node. The second current terminal is coupled to a ground terminal. The snubber transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to the switching node. The second current terminal is coupled to the ground terminal. The first pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal. The second pull-down transistor is coupled between the control terminal of the snubber transistor and the ground terminal.

Switching regulator with configurable snubber

A circuit includes an avalanche diode having an anode and a cathode. The circuit also includes a buffer stage having a buffer input, a power input and a buffer output, in which the buffer input is coupled to the anode, and the cathode is coupled to the power input. The circuit includes a transistor coupled between the power input and a clamp output. The transistor has a control input coupled to the buffer output, and a loop circuit is coupled between the buffer output and the buffer input. A capacitor is coupled between the buffer input and an output terminal.

Slew-rate control for transistors

In the described examples, a driver includes a signal controller that provides a gate control signal to a gate buffer coupled to a gate of a transistor and a field plate control signal to a field plate buffer coupled to a field plate of the transistor. The signal controller provides a rising edge on the field plate control signal causing the field plate buffer to provide a bias voltage on the field plate of the transistor a predetermined amount of time after providing a rising edge on the gate control signal that causes the gate buffer to provide a turn-on voltage on the gate of the transistor that causes the transistor to transition from a cutoff region to a saturation region and to a linear region.

Driver for transistor

A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.

Series capacitor buck converter having circuitry for precharging the series capacitor

Methods, apparatus, systems and articles of manufacture are disclosed to adjust a transient response. An example apparatus includes a clamping circuit including a first input, a second input, a third input, and an output, wherein the first input is adapted to be coupled to a selector, a reference voltage generator including an output, wherein the output of the reference voltage generator is coupled to the second input of the clamping circuit, an error amplifying circuit including an output, wherein the output of the error amplifying circuit is coupled to the third input of the clamping circuit, and a pulse width modulator including an input, wherein the input of the pulse width modulator is coupled to the output of the clamping circuit.

Methods and apparatus to adjust a transient response

A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver for receiving communications from the secondary side wireless power receiver through the inductive coupling comprises a primary side tank circuit receiving a signal on from the secondary side wireless power receiver. A phase delay or time delay circuit generates a fixed delay clock signal. A sample and hold circuit samples a tank circuit voltage utilizing the fixed phase or time delayed clock signal. A comparator is coupled to an output of the sample and hold circuit for extracting data or commands from the signal stream. A method of operating a primary side wireless transmitter inductively coupled to a secondary side wireless power receiver for supplying power to the wireless power receiver to power a load coupled to the receiver is also disclosed.

Circuit and architecture for a demodulator for a wireless power transfer system and method therefor

Methods and apparatus to increase efficiency of a power converter using a bias voltage on a low side drive gate are disclosed. An example power converter includes an inductor; a transistor coupled to the inductor; and a driver coupled to a gate of the transistor, the driver to apply (A) a first voltage to the gate to enable the transistor, (B) a second voltage to the gate to disable the transistor, and (C) a third voltage to the gate during a transition between applying the first voltage and the second voltage, the third voltage being between the first voltage and the second voltage.

Increasing efficiency of a switched mode power converter

A method includes determining that a current at an inductor in a series transfer capacitor buck converter is decaying to zero during a first cycle. The method also includes, in response to determining that the current at the inductor is decaying to zero, enabling an electrostatic discharge (ESD) structure and turning off a low side transistor. The ESD structure is disposed at a node connecting the low side transistor, a high side transistor and the inductor. The method further includes disabling the ESD structure before the high side transistor is turned on during a next cycle following the first cycle.

Method and apparatus for inductive-kick protection clamp during discontinuous conduction mode operation

A power converter includes at least a first phase including a high-side MOSFET transistor (HSA) and a low-side (LS) MOSFET transistor (LSA) driving a first output inductor. The first phase further includes an active gate drive assist circuit including first MOSFET switch (first switch) and second MOSFET switch (second switch) positioned in series between a source of HSA and a drain of LSA. A capacitor (CS) is between the source of HSA and drain of LSA. A bootstrap capacitor (CA) having a reference terminal is connected to a node between the first switch and the second switch.

Switched reference MOSFET drive assist circuit

Growing community of inventors

Bedford, NH, United States of America

Joseph Maurice Khayat