Hewlett Packard Enterprise Development LP

Silicon Graphics, Incorporated

Other

Cray Research, Inc.

Silicon Graphics International Corporation

Joseph Martin Placek

Russell Leonard Nicol

Gregory Michael Thorson

Mark Ronald Sikkink

Randal Steven Passint

Donglai Dai

Frank Nolan Cornett

Philip Nord Jenkins

Terrance L Bowman

John Francis De Ryckere

Paul R Frank

Rodney A Ruesch

Eric P Lundberg

Nan Ma

John F DeRyckere

Michael R Arneson

Karen Rae Beighley

Brian T Hillert

Russell L Nicol

Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.

Method and system for high speed data links

Methods and devices for reducing the latency associated with retransmitting data packets are provided. A device used to receive data packets may include physical layer circuitry and data link layer circuitry communicatively coupled to the physical layer circuitry. The data link layer circuitry may include an Automatic Repeat reQuest (ARQ) processing circuit to send requests for retransmitting data packets. The data link layer circuitry may also include a Forward Error Correction (FEC) processing circuit to receive decoded data packets from the physical layer circuitry, to perform error correction on packets received by the physical layer circuitry, and to provide a correction status signal to the ARQ processing circuit indicating whether or not a particular decoded data packet received from the physical layer circuitry contains one or more incurable errors.

Communications having reduced latency

An apparatus and method detects trapped data at an intermediate node in a network path between a source node and a destination node, and re-routes that data to a downstream intermediate node in the network path via an alternate network path. An apparatus and method may include a virtualized physical interface, and may redirect the trapped data through a system's packet switched network, or through a system's flit switched network.

Adaptive routing for link-level retry protocol

A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals.

High speed serial link in-band lane fail over for RAS and power management

A system for establishing a primary master node in a computer system includes a plurality of nodes, each node configured with an update interval, a hierarchy of master nodes selected from the plurality of nodes, wherein the master nodes are configured to synchronize the plurality of nodes with a clock value by sending out its clock value when its update interval has expired, wherein each node resets its update interval when it receives the clock value, a primary master node selected from the hierarchy of master nodes based on its update interval, and at least one backup master node selected from the hierarchy of master nodes based on its update interval, the backup master node configured to become the primary master node when the plurality of nodes do not receive the clock value after a predetermined period of time has elapsed.

System and method of synchronizing real time clock values in arbitrary distributed systems

A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.

The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.

Method and apparatus for communicating computer data from one point to another over a communications medium

A variable communication systems comprising a plurality of transceivers and a control circuit connected to the transceivers to configure the transceivers to operate in a bi-directional mode and a uni-directional mode at different times using different transfer methods to transfer data.

Variable mode bi-directional and uni-directional computer communication system

A client interface supporting a plurality of peripheral channels and a network channel. The peripheral channels include a maintenance channel, message input channel, message output channel, express channel and several DMA channels. The client interface routes packets from the network to the peripheral resources and prioritizes the dispatching of packets onto the network. Express packets and message packets are given priority over DMA type packets. Priority to dispatch is rotated among the DMA channels.

Growing community of inventors

Chippewa Falls, WI, United States of America

Joseph Martin Placek