International Business Machines Corporation

The Panda Project

Joseph M Mosley

Jack A Dorler

Stephen Douglas Weitzel

Claude Louis Bertin

Wayne John Howell

Robert G Baker

George J Jordy

Vito J Tuozzolo

Maria M Portuondo

Gene J Gaudenzi

John Farley Ewen

Mohanlal Savji Mansuria

Richard D Musa

Yuen H Chan

Peter Anthony Franaszek

Christos J Georgiou

Howard Thomas Olnowich

John D Davis

Harsaran S Bhatia

Michael O Jenkins

Thomas Basilio Genduso

Santosh Prasad Gaur

John S Lechaton

Robert Francis Lusch

Mark Budman

William Frederick Shutler

Gurumakonda R Srinivasan

Robert V Jenness

Walter S Klara

Allan L Mullgrav, Jr

Lloyd H Massman

Gerald A Maley

Edward F Culican

Theodore William Kwap

Susan L Tempest

Donald B Mooney

Philip E Pritzlaff, Jr

Erich Berndlmaier

Anthony D Wutka

John C Milliken

Richard O Seeger

Walter N Zalph

Drew L Taylor

Kristen A Hausman

Roland Joseph Auber

James E Dickerson

Clarence I Peterson, Jr

Philip F Noto

Scott A Mc Cabe

A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays&mdash;on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.

All-node switch-an unclocked, unbuffered, asynchronous switching apparatus

An electronic module includes multiple stacked bare IC chips ('a stack') and a sensor assembly that is mechanically coupled to an end surface of the stack. Electrical connection between the sensor assembly and the stack is provided by a metallization layer disposed on a side-surface of the stack. Specifically, wiring of the sensor assembly extends to an edge surface thereof corresponding to the side-surface of the stack where it electrically connects to the side-surface wiring. The IC chips of the stack are similarly electrically connected to the side-surface wiring. Multiple sensors (e.g., CCD arrays) may be electrically and mechanically coupled to multiple surfaces of the stack for providing a, e.g., multi-view imaging module. Multiple electrical and mechanical options exist for the connection of sensors to stacks within electronic modules.

Multi-view imaging apparatus

Packaged electronic module and integral sensor array

A semiconductor die carrier configured to be secured to a printed circuit board includes an insulative package for housing a semiconductor die. The insulative package has a top surface, a bottom surface, and a plurality of side surfaces coupling the top surface and the bottom surface. At least one row of electrically conductive leads extends from at least one of the side surfaces of the insulative package. Each of the leads has a proximal end, at least one horizontal portion extending in a horizontal direction, at least one vertical portion extending in a vertical direction, and a distal end. The distal ends of the leads are configured to be secured to the printed circuit board such that, when the distal ends of the leads are secured to the printed circuit board, at least a portion of the insulative package is located below an upper surface of the printed circuit board.

Low profile semiconductor die carrier

A semiconductor die carrier includes an insulative module; a plurality of electrically conductive leads extending from the insulative module; a semiconductor die housed with the insulative module; and at least one high frequency capacitor secured to the insulative module for facilitating transmission of high frequency signals carried to and from the semiconductor die on the electrically conductive leads.

Semiconductor die carrier having a dielectric epoxy between adjacent

A processor clock (302) is momentarily synchronized to a subsystem clock (307) during transfers of data between a processor (301) and a subsystem (305). After the completion of the data transfer, synchronization is disabled and the processor clock runs asynchronously at its own internal frequency, which is higher than the subsystem clock frequency. In one embodiment, the processor clock uses a free running ring oscillator (401) that is constructed on the same integrated circuit chip as the processor. Changes in temperature and power supply voltage not only cause changes in the maximum operating speed of the processor, but they also cause corresponding changes in the frequency of the processor clock. Thus, the frequency of the processor clock tracks changes in the maximum operating speed of the processor caused by temperature and power supply variations.

Processor with free running clock with momentary synchronization to

Electronic modules with integral sensor arrays

A trackball pointing device has a housing of a size that can be readily held in the hand of a user. The housing includes a top wall upon which are mounted a trackball and buttons for manipulation by a user's thumb. A cable passes emerges from the bottom wall of the housing. The bottom wall includes a plurality of channels extending in different directions from where the cable passes through the housing wall. Each channel is recessed and has strain relief tabs therein so that the cable can be placed in one of the channels and releasably held in place by the tabs. A user can locate or place the cable in the one of the channels most suitable to the user.

Pointing device with relocatable cable

A network protection method and apparatus are disclosed for alerting an operator when a terminal device is disconnected from the network. A network controller adapter is connected to a network control computer. The network controller periodically stops normal data communication and scans some or all of the network ports to ascertain the present and absent status of a terminal device at each port. Status is detected by passing a current through a port and measuring the feedback voltage. If the status changes between scans, an operator is alerted by sounding an alarm at the network control computer or by other steps such as dialing a telephone number and transmitting a stored message or by transmitting an alarm message over the network to one of the terminal devices such as a personal computer.

Network connected device protection

A flexible cable assembly for coupling an electronic apparatus, having a port for receiving personal computer cards in accordance with the PCMCIA standard, to at least one peripheral device, said flex cable assembly comprises a personal computer card connector, in accordance with the PCMCIA standard, for connecting into a corresponding port in the electronic apparatus, and a flexible cable connected to the personal computer card connector. The personal computer card connector also comprises an interface to said at least one peripheral device. In accordance with a further aspect of the invention, the flex cable assembly can also couple a first electronic apparatus, to a second electronic apparatus, each having a port for receiving personal computer cards in accordance with the PCMCIA standard. This flex cable assembly comprises (1) a first PCMCIA card connector for connecting into a corresponding port in either the first or second electronic apparatus; (2) a second PCMCIA card connector for connecting into a corresponding port in either the first or second electronic apparatus; and (3) a flex cable coupled between the first and second personal computer card connectors.

All flex PCMCIA-format cable

An electrical device for logic circuits having a package comprising a combination of controlled collapse electrical interconnections, such as solder balls and pin through-hole conductors, wherein the conductors are disposed outside the perimeter of an inter-array of solder balls, which when a maximum number of solder balls are disposed, the array is circular in shape, so as to provide an increased footprint for the electrical device beyond that, otherwise maximum footprint for solder balls alone, which footprint is otherwise limited in size due to failures which occur in solder balls when solder balls are exposed to thermal and mechanical stress levels at extended distances from the neutral or zero stress point of the array.

Surface mount chip package having an array of solder ball contacts

A thermoelectrically cooled integrated circuit package including an insulative module which defines a cavity, a thermoelectric cooler within the cavity, and an integrated circuit chip connected to the thermoelectric cooler, thus providing an integrated circuit package in which the integrated circuit package itself dissipates thermal energy generated by the integrated circuit chip.

Integrated thermoelectric cooling

A thermoelectrically cooled integrated circuit package is provided which includes a thermally conductive dielectric substrate, an input connecting portion and an output connecting portion supported by the dielectric substrate, and an integrated circuit chip including an input terminal and output terminal. The input terminal is electrically connected to the input connecting portion via a first conductive material, and the output terminal is electrically connected to the output connecting portion via a second conductive material. The first conductive material and the second conductive material thermoelectrically cool the integrated circuit chip when a signal passes through the first conductive material and the second conductive material.

Thermoelectric cooling via electrical connections

Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path. The NOR gates are implemented as a differential amplifier (FIG. 5) having two transistors (610 and 612) in the input leg and one transistor (616) with its base connected to a regulated voltage (Vr) in the opposite leg. The output of the NOR gate is taken from the collectors of the input transistors. The propagation delay of the oscillator signal through the gate is minimal because, to switch the output state of the gate, only the state of one of the input transistors (610 or 612) must be changed. The short propagation delay through the gate permits high frequency operation, as well as the ability to program small incremental steps in the center frequency of the oscillator.

Programmable voltage controlled ring oscillator

A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Analog macro embedded in a digital gate array

Growing community of inventors

Boca Raton, FL, United States of America

Joseph M Mosley