Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Veritech Limited

At&t Bell Laboratories

Joseph M Moran

Gary N Taylor

Dan Maydan

David A Miller

David N Wang

Martin Barry Feldman

Ronald J Schutz

David B Fraser

James Vincent DiLorenzo

Robert E Dean

Gerald A Coquin

Gerard Edward Mahoney

Nadia Lifshitz

Peter A Heimann

William E Benedetto

Thomas C Russell

A hermetic package having connectors, such as optical fibers or electrical leads, connected and bonded thereto with a bonding material such as epoxy resin, has the bonding material coated with a single layer or multiple layers of sealing material, such as chromium, copper, gold, tungsten, titanium, nickel, or aluminum, to prevent outgased material from the bonding material from entering the hermetic package enclosure. The bonding material may be recessed prior to coating of the sealing material to permit the sealing material to be polished from the optical element and the optical element polished flush with the inside of the package while leaving the sealing material covering the bonding material.

Outgas prevention in electrooptical packages

Alignment of an array of N elements, such as optical fibers, within a preselected tolerance value is obtained using a primary substrate with a plurality of N apertures extending therethrough from a first surface to a second opposing surface. Each aperture, at its narrowest point, has a cross-section that is greater than a cross-section of an element to be inserted therethrough. Each of the elements passes through its corresponding aperture and rests against the same corresponding point and/or sidewall of the aperture so as to result in the desired alignment. A directing arrangement directs the elements toward the primary substrate at a predetermined angle to cause a spring-like action to occur in each of the elements when threaded through its associated aperture for aligning the elements to engage the same corresponding point and/or sidewall of the aperture.

Optical fiber array and method of aligning optical fibers in the array

Preselected alignment of an array of N optical fibers is obtained using a relatively thick primary substrate with a thin layer mounted thereon. The primary substrate has a sufficient structure to support an array of N spaced-apart optical fibers passing therethrough. The primary substrate has first and second opposing surfaces and defines a plurality of N primary substrate apertures which each extend therethrough from the first surface to the second surface and have a cross-section which is greater than a cross-section of an optical fiber such that one of the N optical fibers can be inserted through each of the N primary substrate apertures. The layer is metal, is relatively thin, and engages one of the first and second opposing surfaces of the primary substrate, and defines N layer apertures therethrough. Centers of the layer apertures are aligned to a preselected tolerance value which is required for the array of elements.

Optical fiber array and method of formation

Electronic devices such as hybrid integrated circuits such as those having test points spaced less than 1250 .mu.m are advantageously evaluated utilizing a two-probe process. In this process the probes are moved between test points in a pattern that reduces movement distance without concern for any ordering imposed by the nets themselves or the test to be made. Additionally, the test is made so that the movement time is the limiting factor.

Testing process for electronic devices

An apparatus for testing of electrical circuits has a buckling beam probe assembly having advantageous features that make it useful for contacting area arrays of test points, and for reliably establishing contact therewith. The probe elements remain essentially parallel even in the buckled state, and the probe tips execute a small 'wiping' movement on the contact point. In some preferred embodiments the probe tips are shaped to result in reduced contact area.

Apparatus having a buckling beam probe assembly

A new method for fabricating a device, such as a semiconductor device, is disclosed. The method includes the step of patterning a substrate with a trilevel resist containing a spin-deposited substitute for the conventional central, silicon dioxide region. This substitute includes an organosilicon glass resin in combination with metal-and-oxygen containing material. The inventive method prevents the losses of linewidth control, and avoids the pattern degradation due to undesirably many pinholes, of previous such methods.

Device fabrication method using spin-on glass resins

The invention involves new etch monitoring and thickness measurement techniques which are more accurate than previous techniques. In accordance with the invention, the etch depth of a substrate region undergoing etching is monitored, or the thickness of the region is measured, by impinging the region with light and detecting the intensity of the reflected light. In contrast to the previous techniques, the incident light is chosen so that a substrate region underlying, and/or a patterned substrate region overlying the substrate region of interest is substantially opaque to the incident light, which precludes the formation of signals unrelated to etch depth or thickness.

Interferometric methods and apparatus for device fabrication

In a plasma-assisted dry etching process designed to pattern VLSI devices, a relatively high and uniform etch rate exhibiting low contamination is achieved over the entire surface extent of each wafer to be etched. This is accomplished by mounting the wafers in a unique fashion on one of two spaced-apart electrodes in the reaction chamber of a dry etching system. In particular, the front surface of each wafer is maintained in substantially the same plane as that of surrounding dielectric material. Additionally, the thickness of the surrounding dielectric material is designed to be considerably greater than the thickness of any dielectric material in contact with the back surface of each wafer. In that way, the entire front surface extent of each wafer is influenced by a relatively uniform electric field. Moreover, the available field in the chamber is in effect focussed onto the wafer surfaces, thereby achieving a relatively high etch rate characterized by low contamination.

Etching apparatus and method

In a plasma-assisted etching apparatus and method, surfaces in the reaction chamber are covered with a layer of a polyarylate polymer. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Apparatus and method for plasma-assisted etching of wafers

In a VLSI device fabrication process, erosion of a patterned resist layer (16, 18) during dry etching of an underlying layer (14) can significantly limit the high-resolution patterning capabilities of the process. As described herein, a protective polymer layer (60, 62) is formed and maintained only on the resist material (16, 18) while the underlying layer (14) is being etched. High etch selectivities are thereby achieved. As a consequence, very thin resist layers can be utilized in the fabrication process and very-high-resolution patterning for VLSI devices is thereby made feasible.

High-selectivity plasma-assisted etching of resist-masked layer

In an integrated circuit fabrication sequence, a relatively thick sacrificial layer (18) is deposited on a nonplanar surface of a device wafer in which high-resolution features are to be defined. The thick layer is characterized by a conforming lower surface and an essentially planar top surface and by the capability of being patterned in a high-resolution way. An intermediate masking layer (22) and then a thin resist layer (20) are deposited on the top surface of the sacrificial layer, the thickness of the resist layer being insufficient by itself to provide adequate step coverage if the resist layer were applied directly on the nonplanar surface. A high-resolution pattern defined in the resist layer is transferred into the intermediate masking layer. Subsequently, a dry processing technique is utilized to replicate the pattern in the sacrificial layer. A high-resolution pattern with near-vertical sidewalls is thereby produced in the sacrificial layer. By means of the patterned sacrificial layer, high-resolution features are then defined in the underlying nonplanar surface.

Fabrication of integrated circuits utilizing thick high-resolution

A mixture of poly(2,3-dichloro-1-propyl acrylate) and poly(glycidyl methacrylate-co-ethyl acrylate), with the latter forming between 1 percent and 20 percent by weight, of the total polymer mixture, has been found to form an x-ray resist having adhesive and resolving properties superior to those of poly(2,3-dichloro-1-propyl acrylate) which is a good x-ray resist material. Superior properties of the mixture are attributed to the fact that the two polymers form a compatible polymer mixture which is a relatively rare and unpredictable event in polymer chemistry.

X-ray resist containing poly(2,3-dichloro-1-propyl acrylate) and

X-ray lithographic systems as heretofore constructed include a low-attenuation chamber for propagating x-rays from a source toward a mask member that is positioned in close proximity to a resist-coated wafer. Both the mask and the wafer are included in the chamber which typically is either filled with helium or evacuated to a pressure less than about 10.sup.-2 Torr. In accordance with this invention, an x-ray lithographic system is constructed to enable establishment in the wafer-to-mask region of a controlled atmosphere that is separate and distinct from that maintained in the low-attenuation chamber. In this way, an improved lithographic system with advantageous throughput and other characteristics is realized.

X-ray lithography

An integrated high-power gallium arsenide field-effect-transistor device for operation in the gigahertz range comprises a multiple-gate structure. The device, which features gate cross-under fingers, is fabricated in microminiature form by directly processing a wafer using electron-beam lithographic techniques.

High power gallium arsenide schottky barrier field effect transistor

In pattern generating apparatus of the type employing a reciprocating laser beam for scanning a substrate surface, three scan lines are formed simultaneously. During reciprocation in one direction, the beam is deflected upwardly at an angle of arccot (1/3) with respect to the reciprocating direction, and during reciprocation in the opposite direction, the beam is deflected downwardly at an angle of arccot (1/3).

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Berkeley Heights, NJ, United States of America

Joseph M Moran