Motorola Corporation

Joseph M Harris, Ii

John P Dunn

James C Nash

Tony Tong-Khay Cheng

Theo C Freund

An integrated circuit (10) contains a central processing unit (CPU) (12) and a plurality of memory blocks (26-34) configured into one or more banks of memory. A plurality of power control switches (38-42) are used to dynamically select which of a plurality of external voltage supply signals are provided to power each of the memory blocks (26-34). The power control switches (38-42) may be configured from software via writing the data to a register (24) or can be enabled by test control circuitry (22) or can be automatically enabled in response to VDD power voltage failure. In addition, an intelligent controller can dynamically control the switches in response to execution flow of data accesses and instruction fetches from the memory banks so that only currently accessed memory banks or recently accessed memory banks are activated at a high power level while all other memory banks are in a low power stand-by mode.

Integrated circuit having standby control for memory and method thereof

A method and apparatus for allowing the soft defect detection testing (SDDT) of an memory array (106) of a data processor (100) begins by providing a control value to a memory controller (111). The control value determines whether a switching circuit (104) will apply a VDD power supply voltage from a VDD terminal (132) or a Vstby power supply voltage from a Vstby terminal (130) to a selected portion of the memory array (106). When in an SDDT test mode, the selected portion of the memory array (106) is supplied by the Vstby terminal (130). While being supplied by the Vstby terminal (130), the selected portion of the memory array (106) is SDDT tested by coupling a current detection device to the pin (130) and measuring a current I drawn by the selected portion of the memory array (106).

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Cedar Park, TX, United States of America

Joseph M Harris, Ii