Linear Technology Corporation

Sipex Corporation

Joseph L Sousa

Andrew Joseph Thomas

David M Thomas

Jeffrey B Van Auken

Alfio Zanchi

Jesper Steensgaard-Madsen

A flux beam is generated as a function of flux magnitude patterns. A plurality of flux signals is detected via a sensor array comprising a plurality of sensors. A plurality of flux patterns is generated based on the plurality of flux signals, each of the plurality of flux patterns representing a respective one of the plurality of flux signals. A plurality of flux magnitude patterns is generated based on the plurality of flux patterns, each of the plurality of flux magnitude patterns representing an absolute value of a respective one of the plurality of flux patterns. A flux beam is then generated as a function of the plurality of flux magnitude patterns.

Flux beamforming

Circuits and methods for maintaining a substantially constant input and output current for a charge pump circuit are provided which reduce current variation during switching intervals. The charge pump circuitry of the present invention maintains a current flow path from a current source to the charge pump output which minimizes or eliminates spikes normally associated with the switching intervals.

Charge pump with reduced current variation

A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.

Time-multiplexed residue amplifier

A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal.

Complex-admittance digital-to-analog converter

Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.

Circuits and methods to reduce or eliminate signal-dependent modulation of a reference bias

Systems and methods for reducing the magnitude of signal dependent capacitance are provided. Capacitance canceling circuitry is operative to generate cancellation capacitance in response to the magnitude of a signal, which may be the same signal that produces the undesired signal dependent capacitance, to at least partially cancel the signal dependent capacitance.

Circuits and methods for canceling signal dependent capacitance

A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.

CMOS switch with linearized gate capacitance

The circuits and methods of the present invention provide sample and hold circuits that incorporate an auxiliary sampling leg that cancels distortion produced in a main sampling leg of the sample and hold circuit. The auxiliary sampling leg of the circuit produces canceling distortion that is proportionally larger than the distortion produced in the main sampling leg. The distortion in the auxiliary sampling leg is then reduced in size so that the canceling distortion becomes proportionally equal to the distortion in the main sampling leg. Finally, the proportionally equal canceling distortion of the auxiliary sampling leg is subtracted from the distortion of the main sampling leg so that substantially all of the distortion is canceled out while retaining a substantial portion of the input signal.

Circuits and methods for canceling harmonic distortion in sample and

A full differential sample and hold circuit for an analog to digital converter. The sample and hold circuit samples and holds the differential signal resulting from two input signals. The sample and hold circuit includes a comparator, two differential capacitors and a common mode sample and hold circuit. The comparator has two input terminals and an output terminal. Each of the differential capacitors corresponds to one of the input signals and has an input terminal adapted for selective coupling to the respective input signal. Each of the differential capacitors has an output terminal electrically coupled to a different input terminal of the comparator. The common mode sample and hold circuit is disposed between the input terminals of the two differential capacitors. In one embodiment, the common mode sample and hold circuit comprises two common mode capacitors. Each of the common mode capacitors has an output terminal electrically coupled to a reference voltage and an input terminal electrically coupled to the input terminal of a different differential capacitor. In another embodiment, the reference voltage is ground. The invention also relates to a method of sampling and holding a differential signal.

Differential sample and hold circuit with common mode sampling for an

A multiple channel analog to digital converter utilizing common conversion circuitry for converting multiple analog signals into corresponding digital signals. The converter includes an input stage having a plurality of capacitors, each one corresponding to one of the analog signals. The capacitors sample the respective analog signals and are successively coupled to common conversion circuitry, including a CDAC and a comparator. The CDAC iteratively increments or decrements the voltage of a selected one of the sampled analog signals for comparison to a reference voltage by the comparator. The comparator output is latched by a successive approximation register to provide a parallel output signal which is fed back to control the CDAC.

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Lawrence, MA, United States of America

Joseph L Sousa