Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Dmel Incorporated

Joseph Ku

James Robert Eaton

Stuart Siu

Paul Ouyang

Donald Liusie

Chandrakant D Patel

Salil Pradhan

Geoff M Lyon

Paul S Keltcher

Padmanabha I Venkitakrishnan

Paul Vande Voorde

Stephen Richardson

Shankar Venkataraman

Gary Vondran

A printed circuit board (PCB) includes an antenna for an RFID chip. An RFID chip for a tag is operable to be placed on the PCB such that the RFID chip is connected to the antenna and is operable to use the antenna to transmit data.

Printed circuit board with RFID antenna

The invention includes an apparatus and method of selecting memory cells within a memory array. The method includes receiving a memory cell address. A column address and a row address are generated from the memory cell address. Row select lines or column select lines are pre-charged. A self-timed charging circuit is initiated to provide an adequate amount of time to charge a selected row, and to initiate elimination of static current flowing to unselected rows after a self-timed delay. The other of the row select lines or the column select lines are then pre-charged. Memory cells are selected based upon the column address and the row address. One of two states of the memory cells can be based upon sensing threshold voltages of sense lines that correspond with the selected memory cells.

Self-timed memory device providing adequate charging time for selected heaviest loading row

A system includes a reader operable to read information from an RFID tag. The information includes a configuration of an item. A computer system is connected to the reader. The computer system is operable to store the information read from the RFID tag. The computer system is also operable to create a record of service performed on the item, and write the record to the RFID tag using the reader.

Storing configuration information and a service record for an item in an RFID tag

A system and method for thermally testing integrated circuits, comprising a temperature generation device located within the IC, configured with a primary purpose of affecting a temperature at the IC. A temperature sensor is located within close proximity to the IC, and a temperature controller is coupled to the temperature generation device and to the temperature sensor.

Method and apparatus for thermally assisted testing of integrated circuits

The apparatus and method for forming de-coupling capacitors on top of SOC VLSI chip. The introduced large amount of de-coupling capacitor is intended to solve the power delivery problem of highly integrated and powered VLSI chip, especially in the Silicon-On-Insulator (SOI) technology. This invention proposes a design scheme which could utilize virtually unused area to build efficient de-coupling capacitors without introducing additional manufacture cost. This design scheme is especially effective when the VLSI technology is scaled down further.

Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology

Method for precharging word and bit lines for selecting memory cells within a memory array

A system and method for chip testing is disclosed. The present invention's method includes the steps of establishing a communications link between a chip and a computer tester; receiving on the chip an initial test algorithm over a communications link; testing the chip, using a built-in self-test (BIST) circuit on the chip, in accordance with the initial algorithm; collecting a set of failure information in response to testing; and transmitting the failure information from the chip to the computer over the communications link. The present invention's system includes: a communications link; a computer, operating a set of chip testing software; and a chip under test coupled to the computer by the communications link, having, a memory array; and a BIST module for testing the memory array in response to test algorithms received from the computer and transmitting those addresses within the memory array which failed testing.

System and method for chip testing

Power consumption in a circuit is minimized. The circuit includes a pipelined circuit having a plurality of stages. A determination is made as to whether a predetermined period of time has expired. The predetermined period of time being associated with a predetermined period of time to detect a transition of an input or an output of the pipelined circuit. If the predetermined period of time is exceeded, a sequential shut-down procedure is performed on each stage in the plurality of stages of the pipelined circuit so that each stage is shut-down.

Minimizing power consumption in pipelined circuit by shutting down pipelined circuit in response to predetermined period of time having expired

A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.

Digital event sampling circuit and method

Field repairable system-on-a-chip (SOC) devices are possible by including electrically programmable circuits on the device, for example in the embedded memory of the SOC device. The SOC device may undergo a conventional repair process prior to packaging the device for field operation. In addition to the conventional repair process, usage indicator may be marked prior to packaging. In the field, if the embedded memory of the SOC device fails to operate correctly, diagnostic programs may be run to identify the faulty rows and/or columns. Redundant rows and/or columns may be electrically programmed in the field to repair the SOC device. Multiple field repairs can be accomplished by using this invention.

Field repairable embedded memory in system-on-a-chip

Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Chip multiprocessor with multiple operating systems

An apparatus and method for monitoring memory system performance and controlling an operating parameter is provided. A plurality of digital events indicative of memory system operations is detected, from which a subset of digital events to count is periodically selected, the subset being those digital events occurring during a sampling window time interval. Responsive to each digital event of the subset, a transistor is switched on to conduct current from a power supply to a capacitor. The transistor is biased by the capacitor to operate in a constant current region providing a substantially fixed amount of charge added to the capacitor responsive to each digital event of the subset. The operating parameter is controlled responsive to the charge accumulated in the capacitor, representative of the count of digital events in the subset. In one embodiment, the sampling window time interval is selected pseudo-randomly within a periodic base time interval.

Fine-grained thermal control in memory subsystems

The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic gate further includes a plurality of inputs. The plurality of inputs are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of inputs is a first voltage potential. The invention also includes an address decoder. The address decoder includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. An address decoder output is a function of charge on the charge holding device. The address decoder further includes a plurality of address lines. The plurality of address lines are electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.

Low power logic gate

An analog performance monitoring method and circuit arrangement are adapted to count a plurality of digital event pulses. Each digital event pulse controls a switching circuit to pass a substantially fixed amount of charge from a power supply. The charge is accumulated in a capacitor. In one example embodiment, the switching circuit is a transistor biased by the capacitor voltage to operate in a constant current region. The capacitor has a capacity to accumulate charge added from at least 100,000 digital event pulses maintaining bias of transistor operation in the constant current region. A comparator circuit monitors capacitor charge and signals when a quantity of events adding charge to the capacitor reaches a selectable threshold. In another example embodiment, a programmable voltage divider provides a controllable threshold. A reset circuit discharges the capacitor to an approximate ground level. Sampling is used to estimate a population of digital event pulses.

Analog method and circuit for monitoring digital events performance

A high-density low-cost read-only memory circuit is disclosed. Within the memory circuit, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array. The passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.

Growing community of inventors

Palo Alto, CA, United States of America

Joseph Ku