Advanced Micro Devices Corporation

Joseph Kidd

Brian W Amick

Steven Kommrusch

Michael J Osborn

Michael J Tresidder

Aaron Joseph Grenat

Ryan J Hensley

Priyank Parakh

James Raymond Magro

Warren Anderson

Ronald L Pettyjohn

Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Propagation simulation buffer for clock domain crossing

Clock domain crossing buffer

A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Method and apparatus of alternating service modes of an SOI process circuit

A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

Method and apparatus for phase selection acceleration

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Hudson, MA, United States of America

Joseph Kidd