Marvell International Limited

Marvellworld Trade Ltd.

Joseph Jun Cao

Jun Zhu

Ian A Swarbrick

Sheng Lu

Pantas Sutardja

Samitinjoy Pal

Tsung-Ju Yang

Ruoyang Lu

Hongyan Liu

Can Ma

Peter Tze-Hwa Liu

Liping Guo

Scott Furey

David Geddes

Shawn Chen

A method includes, in at least one aspect, designating a first region of a memory device for storing data of a first type and first error correcting code (ECC) data; designating a second region for storing data of a second type and second ECC data; receiving the data of the first type; generating the first ECC data for the data of the first type using a first ECC associated with a first ECC protection level; storing the data of the first type and the first ECC data in adjacent locations of the first region; receiving the data of the second type; generating the second ECC data for the data of the second type using a second ECC associated with a second ECC protection level; and storing the data of the second type and the second ECC data in the second region.

Providing error correcting code (ECC) capability for memory

A method includes, in at least one aspect, determining a relative delay of a signal path with respect to a timing budget; determining that the signal path is active; determining a value of a voltage being supplied to the signal path; and causing an adjustment in the voltage being supplied to the signal path based on the relative delay, the signal path being active, and the value of the voltage being supplied to the signal path.

Universal adaptive voltage scaling system

Systems and methods for timing read operations with a memory device are provided. A timing signal from the memory device is received at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating circuit is configured to open the gating window based on a control signal. The gating circuit is further configured to close the gating window based on a first edge of the timing signal. The first edge is determined based on a counter that is triggered to begin counting by the control signal. At a timing control circuit, the control signal is generated based on i) a count signal from the counter, and ii) a second edge of the timing signal that precedes the first edge in time.

System and method for automatic DQS gating based on counter signal

In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.

Variable length arbitration

System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Systems and methods for dynamically determining a priority for a queue of commands

A system-on-chip including an ingress arbiter module to receive a plurality of service requests from a plurality of devices located upstream to access a resource located downstream. Each of the service requests includes a quality of service value and a first timing budget value specified by the respective device to indicate an amount of time in which the respective service request is to be serviced by the resource. The ingress arbiter module selects a first service request based on the quality of service values, the first timing budget values, and a time delay associated with arbitrating the plurality of service requests and outputting the first service request downstream. A timing budget generator module generates a second timing budget value for the first service request based on the first timing budget value associated with the first service request, and the time delay.

Timing-budget-based quality-of-service control for a system-on-chip

Systems and methods are provided for command execution. A stream-array data structure including a plurality of stream entries is received. One or more head pointers of one or more command chains are obtained from the stream entries. One or more source commands corresponding to the one or more head pointers are obtained in the command chains. A target command is selected from the one or more source commands based at least in part on a priority of the target command. The target command is executed, and removed from the command chains. The stream-array data structure is updated.

Systems and methods for command execution order control in electronic systems

Systems and methods for timing read operations with a memory device are provided. A timing signal is received from the memory device at a gating circuit. The timing signal is passed through as a filtered timing signal during a gating window. The gating window is configured to open the gating window based on a control signal and to close the gating window based on a falling edge of the timing signal. The falling edge is determined based on a counter that is triggered to begin counting by the control signal. The control signal is generated at a timing control circuit after receiving a read request from a memory controller. The timing control circuit is configured to delay generation of the control signal to cause the gating window to open during a preamble portion of the timing signal.

Systems and methods for DQS gating

In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.

Adaptive voltage scaling using a delay line

Devices and systems are described for transmitting data packets over a chip-to-chip communications link. For example, a device includes a hardware replay buffer to store a data packet. The data packet includes an overhead portion and a payload portion. Additionally, the transmitter device includes circuitry configured to record a memory location within the hardware replay buffer corresponding to an interruption in transmission to a receiver device of the payload portion of the data packet through a physical serial communications link. The memory location references an intermediate location of the payload portion of the data packet.

Chip-to-chip communications

In some implementations, a system includes a universal adaptive voltage scaling monitor (UAVSM) and an adaptive voltage scaling (AVS) controller. The UAVSM is configured to delay a first signal generated by a signal path by an adjustable time period, compare the delayed first signal and a second signal associated with the signal path, and provide an error signal indicating a result of the comparison, where the error signal is asserted when the result of the comparison indicates that the delayed first signal is different from the second signal. The AVS controller is configured to provide a first control signal indicating that the voltage is to be increased when the received error signal is an asserted error signal, and provide a second control signal indicating that the voltage is to be decreased when the received error signal is an unasserted error signal and the signal path is active.

A memory controller provides error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to identify an ECC protection level from a plurality of ECC protection levels for data that is to be stored in the memory device, generate ECC data for the data that is to be stored in the memory device using an ECC corresponding to the identified ECC protection level, store the generated ECC data in the cache, and store the data in the memory device.

Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level

In some implementations, a memory controller is configured receive a data word to be stored in the memory, generate error checking and correcting (ECC) information for the data word, the data word and ECC information forming an encoded word, and distribute bits of the encoded word across the plurality of concurrently accessible memory devices in accordance with one or more indications specifying a number of the bits of the encoded word to store in a wordline of each of the plurality of concurrently accessible memory devices, wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, and bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices.

Providing error checking and correcting (ECC) capability for memory

Systems and methods for dynamic priority control

The present disclosure describes apparatuses and techniques for tunneling transaction packets. In some aspects a packet is received from a peripheral device via a first data interface of a device. The packet includes an address for resource access and an identifier that identifies the peripheral device or a function thereof. Based on this identifier, it is determined whether the peripheral device is attempting to access an internal resource of the device or a resource of a host device connected to a second data interface of the device. If the peripheral device is attempting to access the resource of the host device, the packet is routed to the host device via the second data interface without modifying the address for resource access. By so doing, the peripheral device can exchange data with the host device without using address translation.

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Los Gatos, CA, United States of America

Joseph Jun Cao