Motorola Corporation

Joseph Jelemensky

Oded Yishay

Mark R Heene

Daniel W Pechonis

Alexander L Iles

Susan C Hill

Gary L Miller

Clinton C Kuo

Thomas R Toms

Stanley E Groves

Wallace B Harwood, Iii

Ernest A Carter

Ann E Harwood

Javier Saldana

John B Waite

Jeffrey D Quinn

Surendra P Bhattarai

Guruswamy Ganesh

Daniel N DeBrito

Hubert G Carson, Jr

A data processing system includes an embedded controller ( ) having a core ( ), a system bus, nonvolatile memory ( ), and random access memory (RAM) ( ). The RAM ( ) has a non-overlay region ( ) and an overlay region ( ). The overlay region ( ) may be divided into a plurality of partitions. Partitions of the overlay region ( ) may be used as general purpose memory when they are not being used as overlay regions.

Method and apparatus for overlaying memory in a data processing system

Existing chip select comparator logic (42) is used to compare a portion of the address value with a range of chip select addresses to provide a match signal for use by both the chip select logic (70) and a breakpoint logic circuit (50.x). The match signal is generated by the chip select logic circuit and is reused by the breakpoint logic circuit to perform a different and distinct function. By using the match signal and a breakpoint enable bit, the breakpoint logic circuit selectively asserts a breakpoint signal. Subsequently, a central processing unit (12) receives the breakpoint signal and initiates a breakpoint exception operation to determine whether the breakpoint condition is met and whether further action should be taken.

Breakpoint detection circuit in a data processor and method therefor

Data processor (10) configures internal circuitry during execution of a reset operation in response a logic state of a Mode Select signal. If an external bus control (44) determines the Mode Select signal is in a first logic state, configuration data is provided from a mask register (40). The data is transferred to a plurality of configuration registers (50) and, subsequently, to a remaining portion of data processor (10). If the Mode Select signal is in a second logic state, configuration data is provided from a plurality of bus terminals (48). The data is transferred to the plurality of configuration registers (50). The contents of the plurality of configuration registers (50) are transferred to bus interface unit (42) which subsequently transfers the data to a remaining portion of data processor (10).

Reset configuration in a data processing system and method therefor

A mask programmable register (40) determines a default configuration of a data processor during a reset operation. The default configuration is driven to a plurality of external integrated circuit pins (48) of the data processor with weak drivers (528, 534, 540, 546). Then, on an individual pin basis, an external user (11) may choose to allow each integrated circuit pin to remain in a default state or be drive with an external configuration value. When the external user chooses to allow the integrated circuit pin to remain in the default state, an internal default configuration data value provided by the internal mask programmable register is output by the integrated circuit pin. Conversely, when the external user chooses to override the default state, the user may drive the external configuration value to the integrated circuit pin using an external data source.

Flexible reset configuration of a data processing system and method

An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.

Integrated circuit data processor which provides external sensibility of

Method and apparatus for performing read accesses from a counter (40) while avoiding the large rollover error that may occur when the counter (40) is read using more than one read access cycle. In one embodiment, the present invention monitors the most significant bit of the lower portion (44) of counter (40) for a transition indicating that a rollover has taken place. If a rollover has not occurred, read accesses take place in the normal manner. However, if a rollover has occurred during the latency period between a read access from the upper portion (42) of counter (40) and a corresponding read access from the lower portion (44) of counter (40), the read access from the lower portion (44) is inhibited and a default value is placed on the bus (36) instead.

Method and apparatus for performing read accesses from a counter which

A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.

Data processor and method for providing show cycles on a fast

Method and apparatus for performing multiplexed and non-multiplexed bus cycles in a data processing system (10). The present invention allows a data processing system (10) to switch from multiplexed bus cycles to non-multiplexed bus cycles, and vice-versa, without requiring the data processing system (10) to be reset. In one embodiment of the present invention, a single user programmable control bit (90) is used to select whether an external bus cycle will be multiplexed or non-multiplexed. In more complex embodiments of the present invention, the ability to switch between multiplexed external bus cycles and non-multiplexed external bus cycles may be achieved by way of a plurality of user programmable register fields (96, 100, 102, and 104) located in registers 44. The plurality of user programmable register fields (96, 100, 102, and 104) may be associated with one or more chip select signals.

Method and apparatus for performing multiplexed and non-multiplexed bus

A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) should execute an initialization operation or function in a normal mode of operation. The memory system (16) begins execution of the initialization operation of the system (10) in response to both a logic value of a reset signal and a value of an address transferred by an address bus. The memory system (16) automatically terminates execution of the initialization operation in response to the value of the address transferred by the address bus.

Circuitry for automatically entering and terminating an initialization

A memory has a programmable circuit which allows a user to select an amount of redundancy the memory has varying from zero percent to one-hundred percent. A received address is compared by the circuit with a redundancy percentage control signal to determine if the address falls within a redundant portion of the memory. If so, a redundancy enable signal is asserted to allow the memory to utilize the redundant circuitry.

User programmable redundant memory

A serial peripheral interface achieves compatibility with devices having previous such interfaces while singificantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

Queued serial peripheral interface for use in a data processing system

A serial peripheral interface achieves compatibility with devices having previous such interfaces while significantly reducing the amount of intervention required on the part of the controlling data processing device. Many serial transfers are written to a memory by the controlling device together with command and control information. The interface then executes the stored, or queued, transfers autonomously. Features such as programmable transfer length, programmable chip selects, an alterable queue pointer, and others contribute to the flexibility and usefulness of the interface.

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Austin, TX, United States of America

Joseph Jelemensky