Sun Microsystems, Inc.

Joseph James Ervin

Glenn A Dearth

Jorge E Lach

Gyorgy Rubin

Sandip P Barua

John Michael Mulligan, Jr

An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.

Hot-plug link apparatus and method using a direction line to indicate presence of a hot-plug device

A large multimaster IC bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. The bridge may handle bus segment error conditions and particularly a hang on the Port B bus by attempting to cause any device on the bus segment to respond after the bus bridge has attempted to acquire the segment for a first predetermined period of time. If the bus responds within the first predetermined period of time, the bus bridge resets the bus segment.

Method and apparatus for constructing wired-and bus systems

A special bus master, called a configuration host, 'walks' a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the configuration host assigns a bridge ID to each bridge and enters information into internal bridge registers that control the flow of information between bus segments. The configuration host also populates an address bitmap in each bridge in order to complete the bus system configuration. In one embodiment, the bus topology is a tree configuration and the configuration host performs a recursive procedure that configures each branch of the tree. During this configuration process the internal bridge registers and address bitmap in each bridge are populated.

Method and apparatus for configuring multiple segment wired-AND bus systems

A switching apparatus provides an address extension for an environment, such as IC, that uses devices with a limited address configurability. The switching apparatus provides connection between a main bus and one or more secondary busses to which additional devices are connected. The switching apparatus detects an address on the main bus, and determines whether it is intended for a device on a secondary bus. If so, it connects the main bus to the proper secondary bus where the device in question is located. It then translates the address to an address within the limited configurability of the devices, and places the translated address on the secondary bus where the addressed device is located.

Switching apparatus and method for increasing the total number of addressable electronic devices beyond limits imposed by device address sizes

An addressing circuit includes a first set of inputs configured to receive a first set of address signals en route from the set of processors to the memory and defining a least significant address portion. The addressing circuit further includes a second set of inputs configured to intercept a second set of address signals en route from the set of processors to the memory and defining a most significant address portion. The addressing circuit also includes control circuitry configured to output a replacement set of address signals to the memory in place of the second set of address signals. The replacement set of address signals defines either the most significant address portion defined by the second set of address signals when the least significant address portion is outside a predetermined range, or a predefined most significant address portion when the least significant address portion is within the predetermined range.

Systems and methods for addressing memory

One or more bus bridges are used to partition a large IC bus into smaller bus segments. By programming address bitmaps that are internal to each bridge, the various bus segments can be made to appear as one logical bus. In addition, the bus topology can be designed to maximize the ability to isolate faults within a given segment, thereby improving the ability of technicians to diagnose problems in very large IC implementations. In one embodiment, the invention is a unidirectional bus bridge which is designed so that two such bridges can be used in parallel (facing in opposite directions) to implement a fully bi-directional bus bridge. In another embodiment, IC slave addresses are replicated in a single logical IC bus by addressing a tunnel command to a bridge, which command contains an address and causes the bridge to which it is addressed to forward the contained address.

Method and apparatus for interconnecting wired-AND buses

A &ldquo;firewall&rdquo; apparatus is placed between a single bus master device and a multimaster I C bus system. The firewall apparatus transforms all multimaster bus errors into simple NAK errors and isolates the single bus master from the multimaster bus. Therefore the single bus master needs only to retry transactions that receive unexpected NAKs and all complex multimaster issues, such as bus collisions, transaction termination and bus recovery, associated with the actual error that occurred on the multimaster bus are handled by the firewall apparatus. In accordance with one embodiment, when the single bus master attempts to launch a transaction at a time when the multimaster I C bus is busy, the firewall apparatus absorbs the address driven by the single bus master and then stalls the transaction until the firewall apparatus is able to successfully acquire and drive the address on the multimaster bus. The firewall apparatus is implemented in a preferred embodiment by a programmed microcontroller.

Method and apparatus for connecting single master devices to a multimaster wired-and bus environment

In an electronic system with multiple power supplies, a method and apparatus dynamically determines the number of power supplies required to power up the system without overloading any supply. The individual power supplies do not turn on until the determined number of power supplies have received AC power and become operational before attempting a complete system power on. The amount of required power is determined before power up based on the actual power load present. The actual load is determined by sensing load indicators in each load device and computing the total power load. The amount of power from supplies which have received AC power is determined by detecting when AC power has been applied to each power supply and computing the total amount of power available. System power up is delayed when the number of power supplies which have received AC power is insufficient to power the system without an overload situation occurring.

Method and apparatus for powering up an electronic system after AC power has been removed

An apparatus, system, and method for arbitrating for a serial bus in an efficient manner. An arbitration phase includes master devices asserting respective arbitration addresses on the serial bus after initiating communications sequences with a START condition. After the arbitration phase, the controlling master device conveys a data transfer upon the serial bus. The serial bus and the devices connected thereto may operate according to an I,C-compatable protocol. The arbitration address may correspond to a slave address associated with a slave device. Each arbitration address is preferably associated with only one master device. The arbitration address preferably initiates a READ cycle, and the slave device responds with a data byte. The data byte may be stored, discarded, or ignored by the master device, as desired. The arbitration address may not be associated with any slave device coupled to the serial bus. The master device is configured to continue the communications sequence without receiving acknowledge signals from a slave device during or after the arbitration phase. The master device continues the communications sequence with a repeated START condition and repeated address and data phases for the transfer of data. Each arbitration address may be associated with an arbitration device coupled to the serial bus. Acting as a slave device responsive to multiple slave addresses, the arbitration device may accept WRITE data and/or send READ data in response to receiving the arbitration address. The arbitration device properly acknowledges all addresses and data transfers in which it is involved.

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Stow, MA, United States of America

Joseph James Ervin