International Business Machines Corporation

Joseph James Cahill

Robert Russell Williams

Daniel Guy Young

Daniel Mark Dreps

Anand Haridass

Roger Donell Weekly

Charles Luther Johnson

Kaveh Naderi

Timothy John Mullins

James E Smith

Bruce Ralph Petz

Steven D Lewis

David LeRoy Guertin

Embodiments of the present disclosure provide an apparatus for synchronizing a common reference clock over optics. For example, a reference clock from a host device may be frequency adjusted based on a pass-band of an optical link, decoded, and converted into an optical signal, and transferred to a controller of a target device via one or more optical cables. The controller may be used to recover the reference clock using the optical signal, which may be used as a common-reference clock for communications between the host and target devices.

Clock forwarding over optics

An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Structure for enhancing reference return current conduction

A mixed voltage output driver includes an output sensing circuit that senses an output voltage at an output terminal and generates a voltage signal that corresponds to a voltage level at the output terminal. Next, an impedance selection circuit receives the voltage signal and generates a control signal in response to the output voltage having a higher logical uplevel than the mixed voltage output driver. The control signal is then received by an adjustable drive impedance circuit that is also coupled to an input terminal of the mixed voltage output driver and, in response thereto, the adjustable drive impedance circuit modifies an output drive impedance of the mixed voltage output driver. In another advantageous embodiment, the mixed voltage output driver only determines if the output voltage at the output terminal is at a logical uplevel before adjusting the output drive impedance.

Mixed voltage output driver with automatic impedance adjustment

An improved net driver circuit is provided. The net driver circuit includes a control circuit. A bi-directional input/output (I/O) circuit is coupled to the control circuit. The bi-directional input/output (I/O) circuit includes a receiver and a driver. The control circuit monitors the net and responsive to a new changed state of the net being identified, the control circuit enables the driver to drive the net to the new changed state. The receiver senses the current state of the net and the control circuit remembers the previous state of the net. When the net state is the same as the previous state, the control circuit causes the driver to be in a high impedance state.

Receiver assisted net driver circuit

The present invention is a driver circuit for interfacing electronic components which have different supply voltages. The driver circuit includes a source terminal for receiving a source voltage, an output terminal connected to an off-chip electronic component, and a pull up circuit disposed between the source and output terminals for providing a field effect controlled current path between the source terminal and the output terminal. The pull up circuit includes a first transistor in series with a second transistor, the second transistor providing overvoltage stress relief for the first transistor.

Voltage upwardly compliant CMOS off-chip driver

An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. In previous circuits, a stacked arrangement was usually employed where the N-channel pull-down transistor had another N-channel transistor, with gate connected to the voltage supply, in series with it. In this invention, a parallel N-channel or P-channel transistor is employed to shunt part of the current at the beginning of a transition from high-to-low at the output node of the off-chip driver circuit, and thus lower the voltage across the pull-down transistor to a level which will avoid hot-electron degradation. This parallel transistor is small compared to the main N-channel pull-down, and serves to reduce the output node voltage to a level which does not present a likelihood of hot-electron effects in the main pull-down device. Thus, large current flow through the N-channel pull-down is delayed until the voltage is reduced to an acceptable level. At the same time, this delay is not such as would unduly compromise the high speed nature of the circuits.

Off-chip driver circuit with reduced hot-electron degradation

An integrated semiconductor VLSI chip design that increases the number of driver circuits, or groups of driver circuits, that can be simultaneously switched. Timed driver gating signals, or driver enable signals, are used, in conjunction with physical grouping of driver circuits on the chip, to isolate switching drivers from quiet drivers. This construction and arrangement minimizes detrimental effects usually caused by noise that is generated when driver circuits switch.

Growing community of inventors

Rochester, MN, United States of America

Joseph James Cahill