International Business Machines Corporation

Globalfoundries Inc.

Joseph J Oler, Jr

Kenneth Mon Ngai

Anthony W Fazekas

Richard Quimby Williams

Jeanne P Bickford

Erik L Hedberg

Jeanne P S Bickford

Daniel J Nickel

William F DeCamp

Aurelius L Graninger

Howard B Druckerman

James Robert Montstream

Christopher T McEvoy

Laurice Thorsen Earl

Jason Steven Minahan

Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.

Determining intra-die variation of an integrated circuit

Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.

Semiconductor timing improvement

A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.

Design structure for couple noise characterization using a single oscillator

Structure for couple noise characterization using a single oscillator

A method using a generate-and-verify computer program product to generate by repetitive passes a design rules checking computer program, wherein the design rules are described in a file called a runset. The design rules checking program is used for exhaustive testing of VLSI chips for compliance to the design rules of a given VLSI fabrication process. The runset is repeatedly iterated in loop fashion with respect to a testcase file containing groups of layout structures or shapes used for verifying the correctness of the runset. A general purpose shapes processing program creates an error shapes file for storing geometrical errors found in each said layout structure. Two additional shapes are used in the verification process: user boundary shapes for defining areas in which errors are not to be detected for a given design rule, and automated boundary shapes created to surround each said layout structure with a boundary that defines regions where error shapes can occur. An association table is created which is a compilation of the error shapes, user boundary shapes, and automated boundary shapes associated with each layout structure. The association table is processed to determine the correctness of the runset. The runset is modified to correct each valid error. The repetitive passes continue until a final runset is generated. This final runset becomes the input to design rules checking computer program product and customizes the program for a given VLSI fabrication process.

Method for verifying design rule checking software

Growing community of inventors

Jericho, VT, United States of America

Joseph J Oler, Jr