Xemod, Inc.

Rf Micro Devices, Inc.

Sirenza Microdevices, Inc.

Joseph Herbert Johnson

Pablo Eugenio D'Anna

Kevin Wesley Kobayashi

Gregg A Hollingsworth

A field effect transistor (FET) having fingers with rippled edges is disclosed. The FET includes a semiconductor substrate having a front side with a finger axis. A drain finger is disposed on the front side of the semiconductor substrate such that a greatest dimension of the drain finger lies parallel to the finger axis. A gate finger is disposed on the front side of the semiconductor substrate. The gate finger is spaced from the drain finger such that a greatest dimension of the gate finger lies parallel to the finger axis. A source finger is disposed on the front side of the semiconductor substrate. The source finger is spaced from the gate finger such that a greatest dimension of the source finger lies parallel to the finger axis. The drain finger, the gate finger, and the source finger each have rippled edges with an axis parallel with the finger axis.

Field effect transistor (FET) having fingers with rippled edges

Power switch devices for high-speed applications are disclosed. The power switch device includes a depletion mode field effect transistor (D-FET), an enhancement mode field effect transistor (E-FET) and a bipolar transistor. In one embodiment, the E-FET is coupled in cascode with the D-FET such that turning off the E-FET turns off the D-FET and turning on the E-FET turns on the D-FET. Furthermore, the bipolar transistor is operably associated with the D-FET and the E-FET such that turning on the bipolar transistor drives current from the D-FET through the bipolar transistor to the E-FET to provide a charge that turns on the E-FET. The bipolar transistor provides several advantages such as a higher Schottky breakdown voltage for the E-FET and faster current switching speed for the power switch device.

BI-FET cascode power switch

The present invention discloses and claims the Silicon Carbide based Silicon structure comprising: () a Silicon Carbide substrate, () a Silicon semiconductor material having a top surface, and either bonded to the Silicon Carbide substrate via the bonding layer, or epitaxially grown on the Silicon Carbide substrate; and () at least one separation plug formed in the Silicon semiconductor material. The single bonding layer, or either layer of the double bonding layer, is selected from the group consisting of: {a Silicon dioxide layer; a Silicon layer; a carbon layer; a Silicon germanium (SiGe) layer; a tungsten silicide layer; a titanium suicide layer; and a cobalt silicide layer}. The separation plug extends from the top surface of the Silicon semiconductor material into the Silicon Carbide substrate at a separation plug depth level, and is configured to block the coupling between at least two adjacent active/passive structures formed in the Silicon semiconductor material.

High performance active and passive structures based on silicon material bonded to silicon carbide

A microwave transistor structure having a step drain region comprising: (A) a substrate having a top surface; (B) a silicon semiconductor material of a first conductivity type, having a first dopant concentration and a top surface; (C) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (D) at least one horizontal drain extension region of a second conductivity type and having a horizontal drain extension dopant concentration; (E) a step drain region formed in the silicon semiconductor material, and contacting the horizontal drain extension region; (F) a body region of the first conductivity type and having a body region dopant concentration; (G) a source region of the second conductivity type and having a source region dopant concentration; (H) a shield plate region formed on the top surface of the silicon semiconductor material over a portion of the horizontal drain extension region, the shield plate being adjacent and parallel to the horizontal drain extension region; the shield plate being adjacent and parallel to the conductive gate region; and (I) a conductive plug region.

Microwave transistor structure having step drain region

A microwave transistor structure comprising: (1) a substrate having a top surface; (2) a silicon semiconductor material of a first conductivity type; (3) a conductive gate; (4) a channel region of a second conductivity type; (5) a drain region of the second conductivity type; (6) a body of the first conductivity type; (7) a source region of the second conductivity type; (8) a shield plate region formed on the top surface of the silicon semiconductor material over a portion of the channel region, wherein the shield plate is adjacent and parallel to the drain region, and to the conductive gate region; and (9) a conductive plug region formed in the body region of the silicon semiconductor material, wherein the conductive plug region connects a lateral surface of the body region to the top surface of the substrate.

Microwave field effect transistor structure

A microwave transistor structure comprising: (a) a SiC substrate having a top surface; (b) a silicon semiconductor material of a first conductivity type overlaying the top surface of the semiconductor substrate and having a top surface; (c) a conductive gate overlying and insulated from the top surface of the silicon semiconductor material; (d) a channel region of the first conductivity type formed completely within the silicon semiconductor material including a channel dopant concentration; (e) a drain region of the second conductivity type formed in the silicon semiconductor material and contacting the channel region; (f) a body region of the first conductivity type and having a body region dopant concentration formed in the silicon semiconductor material under the conductive gate region; (g) a source region of the second conductivity type and having a source region dopant concentration formed in the silicon semiconductor material within the body region; (h) a shield plate region being adjacent and being parallel to the drain region formed on the top surface of the silicon semiconductor material over a portion of the channel region; wherein the shield plate region is adjacent and parallel to the conductive gate region; and wherein the shield plate extends above the top surface of the silicon semiconductor material to a shield plate height level, and is insulated from the top-surface of the silicon semiconductor material; and (i) a conductive plug region formed in the body region of the silicon semiconductor material to connect a lateral surface of the body region to the top surface of the substrate.

Microwave field effect transistor structure on silicon carbide substrate

The apparatus for assembly of high power hybrid modules including high power semiconductor chips and conventional surface mount technology (SMT) components are disclosed. The vacuum oven is used for creating the permanent electrical connection between each high power semiconductor chip and the high power hybrid module. The soldering reflow process is used to attach each SMT component to the high power hybrid module. The automated high power hybrid modules assembling process yields the high power hybrid modules with excellent thermal properties.

High power hybrid modules assembly using vacuum oven for permanent electrical connections

The glue deposit device and method for automatically mounting a plurality of power devices to a heatsink using a plurality of spring clamps. The fully automated unconventional pick-and-place machine and method utilizing the glue deposit device for assembling the power printed circuit board using the spring clamps are also disclosed.

Glue deposit device for power printed circuit board

A lateral RF MOS device having a combined source connection structure is disclosed. The combined source connection structure utilizes a diffusion area and a conductive plug region. In one embodiment, the diffusion source area forms a contact region connecting the top surface of the semiconductor material to a highly conductive substrate of the lateral RF MOS transistor structure. In another embodiment, the diffusion source area is located completely within the epitaxial layer of the lateral RF MOS transistor structure. The conductive plug region makes a direct physical contact between a backside of the semiconductor material and the diffusion contact area.

Lateral RF MOS device having a combined source structure

A source connection structure for a lateral RF MOS device is disclosed. The connection structure utilizes a conductive plug to connect a source area and a body area of the device with a backside. The usage of a conductive plug eliminates at least one doping area used for connectivity purposes. Therefore, the density of RF MOS devices per unit area of the chip is increased.

Source connection structure for lateral RF MOS devices

A quasi-mesh gate structure for the RF MOS transistor having a conductive plug source-body-backside connection is disclosed. The RF MOS transistor having the quasi-mesh gate structure utilizes significantly shorter feeding gate paths as compared to the long feeding gate paths used in the prior art RF MOS devices. The RF MOS transistor having the quasi-mesh gate structure can utilize the polysilicon gates or silicided gates. This results in simplification of the fabrication process and/or improved performance at high frequencies.

Growing community of inventors

Phoenix, AZ, United States of America

Joseph Herbert Johnson