Intel Corporation

Other

Joseph H Salmon

Robert E Larsen

Hing Yan To

Kuljit Singh Bains

Khandker N Quader

John Maddux

David A Leak

Michael G Hahn

Jasmin Ajanovic

Michael W Williams

Kurt B Robinson

Randy C Steele

Robert J Johnston

Terry L Kendall

Navneet Dour

Santanu Chaudhuri

Dhiraj Parmar

Jeffery D Wilson

Clyde L Johnson

K K Ramakrishnan

Mike W Williams

A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data before performing the error correction operations using the swizzling map.

Memory controller functionalities to support data swizzling

Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.

Method and apparatus for training a memory signal via an error signal of a memory

Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Reliability, availability, and serviceability solution for memory technology

Reliability, availability, and serviceability solutions for memory technology

Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.

Slave I/O driver calibration using error-nulling master reference

A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Method and apparatus for optimizing timing for a multi-drop bus

A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Synthesis of a synchronization clock

Embodiments of the present invention enable the matching of pull-up and pull-down driver strengths of a slave device (DDRII SDRAM), i.e., the P-channel/N-channel driver pull-up/pull-down Ron and also calibrates the P-channel/N-channel pull-up/pull-down drivers in their linear region of operation. Specifically, embodiments of the present invention may use the DDR-II Off Chip Driver (OCD) protocol for calibration, in addition to using circuit techniques to calibrate the slave driver pull-up Ron within 1 LSB of the pull-down Ron.

Circuit and method for calibrating DRAM pullup Ron to pulldown Ron

A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.

Testing IO timing in a delay locked system using separate transmit and receive loops

A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit and testing setup and hold timing parameters. The method including determining a maximum value for a timing parameter and generating a data pattern with the timing parameter having the maximum value. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function.

Method and apparatus for testing high speed input paths

A memory controller for a computer system includes a first memory address bus and a second memory, address bus. The memory controller further includes circuitry that toggles one of the first and second memory address buses at a time. Because only one memory address bus is toggled at once, the first and second memory address buses can share power and ground pins, thereby reducing the number of power and ground pins on the memory controller.

Memory controller with a plurality of memory address buses

A power-up circuit for a multi-voltage chip having two or more electrostatic devices coupled in series between first and second power supply lines, with a first electrostatic device being coupled between a node and the second power supply line. The power-up circuit comprising a MOS transistor coupled between the first power supply line and the node. A voltage divider coupled between the first and second power supply lines controls the conductivity of the MOS transistor. An internal node of the voltage divider is coupled to the gate of the MOS transistor and the divider is configured such that the internal node rises in potential following power-up to regulate the conductivity of the MOS transistor. The MOS transistor changes from a high conducting state to a low conducting state responsive to an increase in potential of the second power supply line following power-up.

Circuit for independent power-up sequencing of a multi-voltage chip

A computer system device includes a data bus that transmits a plurality of bits of data, and a strobe line. The computer system device further includes a strobe signal generator that generates a strobe signal, and a variable delay device that couples the strobe signal generator to the strobe line. The variable delay device selectively delays the strobe signal.

Method and apparatus for operating a synchronous strobe bus

A method and apparatus for reducing leakage currents in a high voltage tolerant I/O buffer. An I/O buffer designed to tolerate high external voltages by blocking such voltages at a passgate in a p-output path that uses a device between a p-driver gate node and a p-gate node of the passgate to ensure that the p-transistor of the passgate is turned on when the p-driver is driving the pad high. A second device isolates the p-gate node of the passgate from the pad until a pad voltage reaches a predetermined level. Once the pad voltage reaches the predetermined level, the device drives the voltage at the p-gate node of the passgate to that of the pad. Maintaining the p-transistor of the passgate on while the p-driver is driving the pad high allows a rapid hard shut-off of the p-driver as the I/O buffer tri-states the pad. Additionally, the second device maintains the necessary voltage protection by insuring a hard shut-off of the p-transistor of the passgate when the voltage at the pad reaches a predetermined level.

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Placerville, CA, United States of America

Joseph H Salmon