Texas Instruments Corporation

Joseph H Neal

Kenneth A Poteet

Karl M Guttag

Roger D Norwood

Duy-Loan T Le

Wilbur Christian Vogley

Steven D Krueger

Anthony M Balistreri

Joseph P Hartigan

Lionel S White, Jr

Bao G Tran

Hiep V Tran

Claude E Tew

James L Conner

Kevin L Kornher

Paul A Reed

Ngai Hung Hong

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

High-speed memory arranged for operating synchronously with a

High speed memory arranged for operating synchronously with a

Data processing system arranged for operating synchronously with a high

Random access memory with latency arranged for operating synchronously

An array of individual elements (10) having reduced control circuitry as compared to existing devices. Sets of elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other elements (11) in that set. Data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all elements (11) in its fanout because only one element (11) in the fanout is switched at a time.

Time multiplexed addressing circuitry

Random access memory arranged for operating synchronously with a

System including a data processor, a synchronous dram, a peripheral

A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. Each memory circuit has a different separate data lead. A row address strobe signal is applied to the memory circuits. A different column address strobe signal is applied to pairs of the memory circuits. Another discrete memory device includes plural dynamic cell arrays, each of the dynamic cell arrays having a terminal for receiving a row address strobe and a different separate data lead. Each of the dynamic cell arrays has a terminal for receiving a different column address strobe signal.

Memory module arranged for data and parity bits

A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. The data memory circuits are arranged to provide a combined data string having a length equal to the sum of the individual data string lengths. Each data memory circuit includes a signal line connected to control transfer of individual data strings. A different data pin is associated with each bit of the combined data string to transfer a datum for output from the memory module. Each signal line is connected to a control pin to receive an external signal for initiating transfer of one of the individual strings from one of the data memory circuits. The module further includes an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines. A first of the additional signal lines is wired in common with the signal line of a first one of the data memory circuits. A second of the additional signal lines is wired in common with the signal line of a second one of the data memory circuits. The additional memory circuit is responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from one of the data memory circuits.

A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

High speed concurrent testing of dynamic read/write memory array

A semiconductor dynamic read/write memory device has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column address is latched when a serial mode is initiated, and the counter steps through the programmed number of bits, starting at the initial address. The number of bits used in the serial mode may be selected by metal-mask programming. To avoid a speed penalty, look-ahead circuitry initiates the set up for serial mode before the controls for this mode are detected.

Dynamic memory with improved address counter for serial modes

An array of rows and columns of memory cells of the virtual ground type employs a cell layout which has one column line per column instead of requiring extra lines for ground. Half of the column lines are used as outputs and half as ground. One output line and one ground line are selected by improved decode circuitry. The cell array is of a continuous web type wherein metal-to-silicon contacts are shared by four adjacent cells.

Virtual ground MOS EPROM or ROM matrix

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Sugarland, TX, United States of America

Joseph H Neal