Lsi Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Legerity, Inc.

Joseph H Havens

Jeffrey Paul Grundvig

Dewayne Alan Spires

Robert John Kopmeiners

Bruce W McNeill

John C Gammel

Bas Driesen

Robert Kuo-Wei Chen

Christopher J Strobel

An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal. The digitally controlled oscillator circuitry further comprises adjustment circuitry capable of applying a phase adjustment to the clock signal in response to a second digital control word.

Digital phase locked loop

A method and disk drive for calibrating a phase of a clock in the disk drive. The phase of the clock in the disk drive is changed such that a rate of change for the phase is substantially constant. A pattern of data is written to a magnetic material in the disk drive after the rate of change for the phase becomes substantially constant and while changing the phase of the clock. A selected phase of the clock at which the pattern of data that is written on the magnetic material has a desired quality is identified using the rate of change for the phase, a first point in time at which a timing mark on the magnetic material is read, a second point in time at which the timing mark is read, and a third point in time at which the pattern of data has the desired quality.

Phase calibration system for disk drives

Methods and apparatus are disclosed for DC offset estimation and for DC offset compensation that collectively reduce or eliminate the distortion of subcarriers due to DC offset in an OFDM receiver. The DC offset estimation is obtained by subtracting a sum of time domain samples of an OFDM symbol for two consecutive OFDM symbols or subtracting a known transmitted OFDM symbol and a frequency domain representation of a received version of the known OFDM symbol (at least one of which is adjusted to compensate for channel distortion). The DC offset compensation is accomplished by removing the estimated DC offset from the received signal. The DC estimation process and the DC compensation process can be connected in disclosed feed-forward or feedback configurations.

Method and apparatus for estimating DC offset in an orthogonal frequency division multiplexing system

An amplifier having an improved output current drive capability includes an input stage and an output stage. An input of the output stage is operatively coupled to an output of the input stage. The amplifier further includes a current regeneration circuit operatively coupled to the input of the output stage in a feedback arrangement, the current regeneration circuit feeding back a current to the output circuit in accordance with a predetermined scale factor, the fed back current being proportional to an input current supplied to the output stage. The input current supplied to the output stage is dynamically adjustable by the current regeneration circuit in response to an input current requirement at the output stage.

Amplifier circuit with regenerative biasing

Tracking percent overload signal as an indicator of output signal magnitude is achieved by measuring the percent of time the envelope of a varying modulated signal is above a predetermined programmable threshold. The technique is implemented by a level detector including an envelope detector along with circuitry for detecting when the envelope has exceeded the programmable threshold. The output of the level detector is sampled and fed to a counter which provides a digital output which indicates the percentage of time the envelope exceeds the set threshold.

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Pinckney, MI, United States of America

Joseph H Havens