Unisys Corporation

Joseph H End, Iii

Todd M Rimmer

Terrence V Powderly

Andrew F Sanderson

Timothy C Sell

A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a second path controller, and a synchronizer. The arbiter is configured to receive the memory requests from the plurality of requesters and identify requests for processing responsive to the requested memory banks. The first and second path controllers are coupled to the arbiter and the plurality of memory banks with the first path controller configured to process the first memory request and the second path controller configured to process the second memory request. The synchronizer is coupled between the first path controller and the second path controller for synchronizing the first and second path controllers such that the first and second memory requests processed by the first and second path controllers, respectively, do not conflict.

Dual active bank memory controller

Numerous shortcomings exist in prior generation adapter cards for supporting remote consoles for multipartition computer systems. Emulation using memory in the adapter card supports some remote functions so that they appear to be resident on the host computer system to each partition. Additionally, the host computer system memory can be used in one mode to support the emulation of extended mode video console support functions. Scoreboarding and hardware compression are used to limit the volume of data required to be updated to support the emulation.

System for support of remote console by emulation of local console with multipath data flow structure

A division operation is simulated by performing multiple subtractions, in parallel, each of which represents the subtraction of a different multiple of the divisor from the dividend. Each subtraction produces a possible remainder value, but only one subtraction will result in a valid remainder&#x2014;the one representing the divisor multiplied by the actual quotient that would result from the division operation&#x2014;and that remainder is then identified as the modulo output of the division operation.

Circuit and method for high-speed execution of modulo division

The present invention is directed to an improved system for creating LZW compressed files by executing the LZW data compression algorithm on a plurality of special-purposed pipelined processing units, each of which contains hardware-embedded control algorithms. The data paths of the plurality of processors, together with the state machines that control the flow of data through them, provide pipelined execution of the LZW algorithm. For example, at the same instant, processor three can be processing a first input byte, processor two can be processing a second input byte, and processor one can be processing a third input byte.

Hardware-based, LZW data compression co-processor

Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line. If the instructions or data are intended for a specific system logic board, its corresponding ME signal line will be enabled to permit the passage of these signals and the resulting TDO signal through the interface enable circuit. This arrangement permits the incorporation of a bussed TAP interface into a system control interface for testing and controlling system logic boards that comply fully with the IEEE 1149.1 standard, while conserving the system controller card backplane pins dedicated to TAP signals, to two pins per system logic board plus four pins for the bussed TAP interface.

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Malvern, PA, United States of America

Joseph H End, Iii