Synopsys, Inc.

Other

Joseph Gregory Rollins

Arindam Chatterjee

Alexei Svizhenko

A netlist may include a set of resistance components of an integrated circuit (IC) design, and may specify a length, a width, and a metal layer of each resistance component in the set of resistance components, and physical locations of circuit nodes connected to each resistance component in the set of resistance components. A process description may specify the resistivity and thickness of each metal layer in the IC design. For a resistance component in the set of resistance components, resistivity and thickness of the metal layer of the resistance component may be determined based on the process description, and an inductance component corresponding to the resistance component may be determined based on the length and the width of the resistance component, the resistivity and the thickness of the metal layer of the resistance component, and the physical locations of the circuit nodes connected to the resistance component.

Calculating inductance based on a netlist

This invention is a portable exercise system capable of performing multiple exercises for strength and endurance training. The key component is the force generation unit (FGU) which is small and light enough to be suspended during the exercise yet capable of producing a force of 50 lbs. The FGU is programmable allowing it to generate various force vs distance, time or velocity profiles. Different handles, cables and attachments can be connected or used with the FGU perform different exercises. The FGU can charge its battery from the user's energy during use. The FGU can communicate bidirectionally with computers and smart phones for setup and to track the user's performance. Multiple FGUs may be used simultaneously each performing a separate function. The entire system is small enough to fit in a drawer or suitcase. The accompanying software can track the user's performance and function as an automated personal trainer.

Compact smart phone enabled system for strength and endurance training

A method for performing parasitic capacitance extraction of an integrated circuit (IC) design includes: defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; performing an initial plurality of random walks from each region using a Monte Carlo field solver; and dynamically allocating an additional plurality of random walks among the plurality of regions, wherein the allocation is based on statistical errors associated with the initial plurality of random walks for each of the regions. Results from the random walks are averaged to estimate parasitic capacitance of the origin net. The method may include performing the random walks for each region in pairs, wherein a first random walk of the pair is selected in accordance with an anti-symmetric probability function, and a second random walk of the pair is antithetic to the first random walk of the pair.

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Henderson, NV, United States of America

Joseph Gregory Rollins