Nvidia Corporation

Other

Joseph Greco

Inderjit Singh

Howard Lee Marks

Joseph Minacapelli

Jonah Matthew Alben

Barry A Wagner

Anthony Michael Tamasi

A TSV of a first semiconductor die may extend from a semiconductor substrate of the first semiconductor die through at least one metallization layer of the die to connect to a metallization layer to supply power to the second semiconductor die. By extending the TSV, resistance may be reduced, allowing for enhanced power delivery to the second semiconductor die. Resistance may be further reduced by allowing for the TSV to connect to a thicker metallization layer than would otherwise be possible. Also, in some embodiments, the TSV may connect to a metallization layer that is suitable for supplying power to both semiconductor dies. The first semiconductor die may be a top die or a bottom die in a face-to-face arrangement. Disclosed concepts may be extended to any number of dies included in a die stack that includes the face-to-face arrangement.

Extended through wafer vias for power delivery in face-to-face dies

A cover or shield for a mobile radio includes a first cylindrical portion configured to fit a first knob, a second cylindrical portion configured to fit a second knob, and a bridge. A first end of the bridge may be fixed to the first cylindrical portion, and a second end of the bridge may be fixed to the second cylindrical portion. The bridge may be configured to orient the first cylindrical portion and the second cylindrical portion in alignment with the first knob and the second knob, respectively. In one example, the first cylindrical portion includes a cut-out configured to allow manipulation of the first knob by an operator of the portable radio. In another example, the second cylindrical portion is shorter than the second knob providing access to an upper section of the second knob by an operator of the portable radio.

Shield for a first responder radio

In accordance with the disclosure, one or both semiconductor dies in a face-to-face arrangement may include a probe pad layer formed on a face of the die to allow the die to be individually tested prior to assembly of the dies. Thus, faulty dies may be discarded individually so they are not included in a composite semiconductor device, thereby increasing device yields. The probe pad layer also allows dies to be matched so that a composite semiconductor device achieves desired performance, which may further increase device yields. In some embodiments, the probe pads of the probe pad layer formed on the face of the die may be used to individually test the die, and may remain inactive, or inert, during operation of the composite semiconductor device.

Face-to-face dies with probe pads for pre-assembly testing

In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.

Face-to-face dies with a void for enhanced inductor performance

Face-to-face dies with enhanced power delivery using extended TSVS

A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

Apparatus, system, and method for graphics memory hub

An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer may define a frame with an outer periphery and an inner periphery.

Method of fabricating a pad over active circuit I.C. with frame support structure

An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.

Growing community of inventors

San Jose, CA, United States of America

Joseph Greco