Freescale Semiconductor,inc.

Nxp Usa, Inc.

Joseph Gergen

Arvind Kaushik

Sourav Roy

Tan Nhat Dao

Sneha Mishra

Jerome Hannah

William C Moyer

Hector Adrian Sanchez

Bryan D Marietta

David B Kramer

Zheng Xu

Amrit Pal Singh

Arvind Raman

Gayathri Bhagavatheeswaran

William D Schwarz

Xiao Sun

Jason T Nearing

David W Todd

James C Holt

Mohit Gupta

Howard Dewey Owens

Craig C Hunter

Pascal Louis Renard

Benjamin Charles Eckermann

David C Holloway

Kaushik Arvind

Chi Duong

In a hardware-accelerated computing systems, calls are made from a processor to an accelerator core. The hardware-accelerated computing system includes a processor core having a stack, an accelerator, and an accelerator scheduler. The computing system is configured to process an accelerator command by the processor core issuing an accelerator command to the accelerator scheduler during execution of a task the accelerator scheduler receiving the accelerator command and requesting data from the stack, the processor sending the requested data from the stack to the accelerator scheduler, the accelerator scheduler sending the requested data to the accelerator and sending a write response to the processor, the accelerator processing the accelerator command, and the processor continuing execution of the task. The processor pauses execution of the task upon issuing the accelerator command and resumes execution of the task upon receiving the write response from the accelerator scheduler.

Hardware-accelerated computing system

A thread management circuit of a processing system stores a thread identifier table and a thread completion table. The thread management circuit receives, from a processor core, a request for execution of a portion of an application by an accelerator circuit. The thread management circuit allocates a thread identifier available in the thread identifier table to the processor core for the execution of the portion by the accelerator circuit. The thread management circuit communicates a response and an acceleration request, both including the allocated thread identifier, to the processor core and the accelerator circuit, respectively. The thread management circuit communicates a thread joining response to the processor core based on a received thread joining request and an indication by the thread completion table that the execution of the portion by the accelerator circuit is complete. The executed portion is integrated with the application based on the thread joining response.

Method and system for accelerator thread management

Systems and related methods are disclosed to manage memory for an integrated circuit including a processor and logic circuitry to manage the memory. The memory includes segments available for storage of data, and the processor stores data within the memory. Logic circuitry is configured to manage the memory, forms a plurality of sections within the segments, and applies tokens to the plurality of sections. Further, for each storage operation, the logic circuitry searches the tokens to identify blocks of continuous available tokens based upon data length, selects a block from the blocks identified in the search, determines a first token for the selected block, and outputs a memory address to the processor based upon the first token. The processor stores the data at the memory address. For one embodiment, the storage operations are associated with storage of data within packets received from network communications.

Hardware-based memory management for system-on-chip (SoC) integrated circuits that identify blocks of continuous available tokens needed to store data

A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Method and apparatus for controlling wake events in a data processing system

A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.

Explicit barrier scheduling mechanism for pipelining of stream processing algorithms

In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.

Event triggered memory mapped access

A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.

Phase locked loop device and method thereof

A data processing system () includes a CPU () and debug circuitry (). CPU () can execute instructions which provide direct input to one or more of trigger circuitry (), multi-function debug counters (), combining logic (), and action select and control logic (). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger () can produce a resulting action or trigger () but only if it occurs in a predetermined order compared to one or more other triggers (). Multi-function debug counters () can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Method and apparatus for debugging a data processing system

Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.

Single instruction for multiple loops

A method and apparatus for identifying and detecting hazards is presented. An executable specification for the architecture is compiled that includes macroarchitecture and microarchitecture information corresponding to each of the instructions supported by the architecture. A table ( ) is constructed from the executable specification that specifies the particular resource utilization parameters associated with each of the instruction types included in the instruction set supported. From this table a resource utilization parameter list ( ) is compiled that indicates the relative times at which resources are needed by each instruction and when these resources are released by the instruction. Comparisons between different entries in the resource utilization parameter list corresponding to the same resource are performed such that potential hazards are detected. A hazard list ( ) is then compiled that includes all of the hazards detected through the comparison operations utilizing the resource utilization parameter list ( ).

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Manchaca, TX, United States of America

Joseph Gergen