Texas Instruments Corporation

Power Trends, Inc.

Joseph Gerard Renauer

Michael G Amaro

Joel Nathan Brassfield

Charles Allen DeVries, Jr

A power supply has a plurality of switching regulators providing a like plurality of regulated output voltages. The oscillators of the switching regulators are synchronized with one another by a synchronization signal. A synchronization signal detector is provided on one or more of the switching regulators to shift the switching frequency of the oscillator to a lower frequency upon detection of a synchronization signal.

Apparatus and method to synchronize switching frequencies of multiple power regulators

A power regulator has an output for regulated power that is connected to supply power to a load. The load can have various electrical characteristics, including requiring a rapid transient response. The transient response amplitude for the power regulator is decreased by adding capacitance at the output, but that slows the response time of the power regulator by lowering the crossover frequency and the phase margin at the crossover frequency. An adjustable gain element imbedded in the feedback network provides an input to permit a builder or user of the power regulator to vary the effective value of impedance elements in the feedback network. The builder or user selectively connects an impedance to the input of the adjustable gain element to thereby adjust the frequency characteristics of the feedback network to thereby adjust output characteristics of the power regulator to compensate for the effects of capacitance added to the power regulator output. The selective connection of various impedances to the input in the variable gain element adjusts the gain in the feedback circuit so to change the frequency of the gain and output phase of the regulator. Proper adjustment of the variable gain raises the crossover frequency and the phase margin, restoring the performance that was degraded by the added capacitance at the output.

Apparatus and method to compensate for effects of load capacitance on power regulator

A DC to DC converter includes multiple stages to share power handling. The stages are connected in parallel paths between the source input and the load output of the power converter. An analog error signal is generated by comparing the load output signal to a reference signal. The error signal is fed to a phase shifting input of a phase lock loop. The phase lock loop is connected to receive a reference clock signal and maintain a relative clock signal shifted in phase from the reference clock signal by an amount depending on the error signal. Digital divider circuits and digital logic circuits are used to produce phase shifted variable pulse width control signals for the stages. The parallel connected power conversion stages equally share the transfer of power from the input source to an output load. A single analog to digital conversion of a single analog error signal to multiple, phase shifted, variable duty cycle clocks is provided.

Digitally synthesized multiple phase pulse width modulation

A power conversion architecture includes one control capable of simultaneous operation with multiple power conversion circuits. The function of the controlling mechanism includes an output signal proportional to one or more inputs to the controlling mechanism for the purpose of maintaining a destination level at a substantially constant value. The function of each power conversion path is to transfer power from a source to a destination in an amount dictated by the controlling mechanism. The function of the parallel power conversion architecture is to proportionally distribute the power transfer between all power conversion paths.

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Joseph Gerard Renauer