Lucent Technologies Inc.

Bell Telephone Laboratories

At&t Information Systems Inc.

At&t Bell Laboratories

Agere Systems Guardian Corp.

American Telephone and Telegraph, Co.

Joseph George Kneuer

Fabio Massimo Chiussi

Vijay Pochampalli Kumar

Rajiv Bhatia

Jean-Jacques Werner

Andrea Francini

Alexander Feiner

Burton R Saltzberg

Jeffrey W Reedy

Gi-Hong Im

Henry S McDonald

David A Poppe

Richard T Wurth

Alexander John Shaw

Kuang-Shin Lin

David R Johnson

Donald B Grust

Randall G Banton

The total implementation complexity of packet schedulers which aim at approximating the Generalized Processor Sharing (GPS) policy is the combination of the complexity of their system-potential function and the complexity involved in sorting the timestamps in order to select the packet with minimum timestamp for transmission. Given that several scheduling algorithms which use a system-potential function of O(1) complexity have been introduced (among them, the Minimum-Delay Self-Clocked Fair Queuing (MD-SCFQ) algorithm achieves optimal delay and excellent fairness properties), the major contribution to the total complexity comes from the task of sorting the timestamps every time a packet is transmitted or received, which is common to all GPS-related schedulers. A method and an apparatus, called the Logarithmic Calendar Queue (LCQ), is disclosed which can achieve a dramatic reduction of the implementation complexity of sorting the timestamps in a GPS-related scheduler, at the cost of very small and controllable degradation of the guaranteed delay bounds. This is achieved by using a plurality of calendar subqueues, each subqueue associated with different granularity for the representation of timestamp values.

Method and apparatus for guaranteeing data transfer rates and delays in data packet networks using logarithmic calendar queues

The adaptive sequential pattern memory search technique only examines the contents of a subset of the total number of memory locations in each search for information representative of a character string. The subset includes a plurality of storage locations and each examination is performed in one concurrent read operation. If the character string is not matched, the memory must be updated to store information representative of the unmatched string. This updating process selects one location from the subset for storing this representative information. Advantageously, an indicator of when each stored representative information last matched a character string is maintained and utilized in the selection process. In addition, to avoid operational errors associated with outputting invalid information from the 'child' of a previously discarded 'parent', an indication of the time each stored entry is created is utilized to remove such invalid information as it is detected in the updating process.

Sequential pattern memory searching and storage management technique

Multicasting of an ingress cell received at one of a plurality of input ports is provided through a switch network to one or more of a plurality of output ports. The received ingress cell includes a data payload and a bitmap segment identifying the one or more output ports to which the data payload is to be outputted. The data payload is stored in an available cell buffer; associated with each cell buffer is a reference counter for storing a number equal to the number of ports to which that ingress cell is to be outputted. The bitmap segment is used to identify output ports to which the data payload is to be delivered, and a plurality of linked list queues in the memory, one for each of the output ports, is established. The bitmap segment is interpreted to identify output ports to which the data payload is to be delivered and an entry is made into the associated linked list output queue. The data payload is transmitted to each of the identified output ports, according to a sequence determined by the entries in the corresponding linked list queue.

Buffering of multicast cells in switching networks

Multicasting of an ingress cell received at one of a plurality of input ports is provided through a multistage switching network to one or more of a plurality of output ports. An ingress cell including a data payload and information identifying output ports of the network is received at one of the input ports of a first stage of the network. A determination is made of the minimum number of first output ports of the first stage of the network to which a single copy of the ingress cell is to be outputted to enable the ingress cell to reach all of the identified output ports. The single copy of the ingress cell is then routed to the minimum number of first output ports of the first stage of the network.

Multicast routing in multistage networks

Multicasting of an ingress cell received at one of a plurality of input ports is provided through a multistage network to a plurality of output ports. The received ingress cell at a first input port includes a data payload and information identifying one or more routing queues to which a single copy of the data payload is to be outputted. A backpressure queue assignment is identified for the first ingress cell, the backpressure queue assignment identifying a backpressure indicator indicative of the congestion level at at least one routing queue of a subsequent stage. Using the backpressure indicator, it is determined if the first ingress cell is to be outputted from one or more of the routing queues. Thereafter, the first ingress cell is outputted from one or more of the routing queues when the congestion level is below or equal to a first threshold.

Multistage network having multicast routing congestion feedback

Distortion and instability due to echoes in conference communications is reduced through the use of an echo estimating filter disposed in a conference bridging circuit. This circuit includes a signal combiner which receives information signals from each of the parties in the conference communications and provides an output signal which is a combination of the received information signals and an echo compensation signal. The echo estimating filter provides this echo compensation signal in response to the combiner output signal. Advantageously, the echo estimating filter can be fixed or adaptive. In the latter case, the adaptation can be in response to the received information signals or to training sequences.

Technique for reducing echoes in conference communications

A multi-stage time division switch interconnects a plurality of processors that individually communicate over one or more channels at various signalling rates. Any processor may initiate a call and request that a connection be set by the switch. The switch assigns one or more time slots to the call and gathers or distributes data over the interconnecting channels through the utilization of polling techniques, thereby creating a virtual circuit through the combination of a time division switch and a polled communication line.

Time slot polling arrangement for multiple stage time division switch

A multi-stage time division switch interconnects processors communicating over one or more channels on time division lines. One of the processors is designated as a common processor to provide the switching 'mapping' information for the various stages of the switch sending the switching information to the memory and logic of each switched stage over dedicated channels which include channels on the time division line emanating from the common processor and time division channels which pass through several switches until the memory of the applicable switch is accessed.

Switching control for multiple stage time division switch

Growing community of inventors

Fair Haven, NJ, United States of America

Joseph George Kneuer