International Business Machines Corporation

Kozio, Inc.

Joseph G Skazinski

Noel Simen Otterness

Brian Dennis McKean

William A Brant

Keith Edward Short

Michael Edward Nielson

William G Deitz

Al Mansur

A system and method for testing input and output paths connected to an embedded processor. Specialized test software operating on the embedded processor creates one or more test workers or threads, each having a specific routine to perform, which are executed in parallel, stressing various communication paths. The results may be analyzed to help in many different ways during the life cycle of the device with the embedded controller.

Embedded Test I/O Engine

Controller for coupling data between a data storage system and a host includes a first processor and a first RAM coupled to the first processor; a first auxiliary processor including a first memory controller and a first cache coupled to the first memory controller, the first memory controller including first interface for coupling with second auxiliary processor including second memory controller and associated second cache and second interface for coupling with first auxiliary processor, first memory controller including logic for treating the caches as single memory; a bus coupling first primary processor and first auxiliary processor; and interconnection channel separate from the bus coupling first interface of first memory controlled and second interface of second memory controller. Interconnection may be an out-of-band channel permitting device-to-device sharing of associated cache memories without requiring data transfer over the bus. Method and computer program product are also provided.

System apparatus and method for storage device controller-based message passing having effective data channel bandwidth and controller cache memory increase

A system, method, and computer program on a computer readable medium for allowing multiple controllers to communicate with other controllers through the use of a routing table are disclosed. The controllers do not need to be directly connected to each other as long as there is a path through other controllers to reach each other. Routing tables used to determine the optimal communications paths between controllers. These techniques are disclosed that allow the controllers to compute the optimal communications path between two controllers. A first technique computes the path which crosses the least number of controllers to reach the controller to which the message is being sent. A second technique is to compute the path which has the least data traffic crossing the controllers and the interconnects. A third technique combines the first two techniques in that it uses both pieces of information, the shortest route and minimal data traffic, to determine an optimal routing path.

System, method and computer readable medium for intelligent raid controllers operating as data routers

Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy. Reduces amount of host write data that has to be mirrored to alternate controller.

System, apparatus and method providing adaptive write policy for disk array controllers

A method and apparatus are provided for dynamically creating an executable image from an Object File Format (OFF) file stored in a reserved area of one of a plurality of data storage devices in a memory system . In the method, a controller having a Programable Read Only Memory (PROM) , Random Access Memory (RAM) and a Central Processing Unit (CPU) is coupled to the plurality of data storage devices . The memory system is initialized using an initial boot sequence stored in the PROM . This initialization can include a hardware discovery sequence to identify all hardware present in the memory system . Data relating to the discovered hardware is read from the OFF file and translated from an object format into an executable image that is assembled in RAM . Optionally, the PROM is an Electronically Erasable PROM (EEPROM) and the assembled executable image is stored in the EEPROM replacing the initial boot sequence.

Dynamic firmware image creation from an object file stored in a reserved area of a data storage device of a redundant array of independent disks (RAID) system

Structure and method for efficient failover and failback techniques in a data storage system utilizing a dual-active controller configuration for minimizing a delay in responding to I/O requests from a host system following a controller failure is described. A stripe lock data structure is defined to maintain reservation status or stripe locks of cache lines within data extents that are part of a logical unit or storage volume. When a controller fails, dirty cache line data of a failed controller is taken over by a survivor controller. The stripe lock data structure is used to process I/O requests from a host system, by the failed controller. The data storage system functions in a single-active configuration until the dirty cache line data is flushed to one or more storage volumes, by the survivor controller. The inventive structure and method provide utilize a storage volume reservation system. The stripe lock data structure is defined in memory within each of the two or more caching controllers. The stripe lock data structure is used to provide consistent information within each of the two or more caching controllers, and the stripe lock data structure is used by a failed controller to process I/O requests from a host system until dirty cache line data is flushed to one or more storage volumes by a survivor controller. Provides a method and structure which minimizes a delay required to begin processing of host I/O request following a controller failure.

System and method for efficient failover/failback techniques for fault-tolerant data storage system

A data storage system includes a pluralierty of controllers in a master/slave N-way controller topology. The master controller is coupled to a host system, and each controller is operatively coupled to one of a plurality of data unit arrays. The plurality of data unit arrays each include a plurality of disk units that are linked together. The linked disk units appear as a continuous logical unit and each data unit array forms a data span, such that the plurality of data unit arrays form N-way data spans. Each controller is adapted to transfer data between the data units and the master controller in response to instructions therefrom based on a data configuration. The data is then transferred between the master controller and the host system. The master controller is adapted to balance I/O requests amongst the plurality of controllers and re-direct an I/O request directed to a failed controller to an active controller. Alternatively, the data storage system includes a plurality of controllers in a peer-to-peer N-way controller topology. Any one active controller is adapted to transfer data between the data units and the host system in response to instructions therefrom and balance I/O requests amongst the plurality of controllers and re-direct an I/O request directed to a failed controller to an active controller. Advantages include automatic copying of the host data to an alternate controller for data protection. In addition, if the spans are setup as a RAID 0&plus;5 or some other similar configuration, the workload is automatically distributed among the various controllers.

Using multiple controllers together to create data spans

This invention describes structure and method for an efficient architecture allowing n-controllers to work together to improve system performance and fault tolerance, when n is greater than two. This invention provides a new type of RAID architecture using operational primitives in a message passing multi-controller environment to solve the problems presented in having multiple controllers distribute a non-uniform workload. This architecture allows for expansion of the I/O processing capability limited only by the efficiency of the underlying message transport method. In simple terms, the inventive technique breaks input/output (I/O) operations into a set of simple methods which can then be passed around as tokens, or pieces of work to be executed by whichever controller has the least amount of work to perform. (I/O operations include all operations needed to perform the tasks of a RAID controller. These include host read/write commands, rebuilds, data migration, etc.) The workload distribution adapts to the available and types of processing resources available in the system. The advantage of this type of architecture is that additional processing resources can be added to the system to address specific areas which need higher throughput without the need to rethink the software architecture.

Apparatus system and method for N-way RAID controller having improved performance and fault tolerance

The invention provides a system structure, method and computer program product for mirroring cache data from a first controller to an alternate controller in a data storage system, where the data storage system is being managed by the controllers in dual active configuration and the first and alternate controllers are also connected to a system drive that includes one or more disk storage devices and the first controller is connected to a first memory, and the alternate controller is connected to a second memory where each controller has an identical memory layout, and a cache line descriptor data structure defined therein and the cache line descriptor data structure is used by each respective controller to track data mirrored by the controller to a memory connected to an alternate controller and the cache line descriptor data structure includes information for reducing the amount of data mirrored to an alternate controller for secondary cache data mirror operations on same originating cache data with respect to a particular cache line and additionally, the cache line descriptor data structure includes information for coalescing multiple cache data mirror operations corresponding to a particular cache line into a single cache mirror operation to the alternate controller.

System, apparatus, and method providing cache data mirroring to a data storage system

Method for storage controllers with different data formats to access common storage configuration information

A storage volume reservation system and method for maintaining cache coherency amongst a plurality of caching controllers in a data storage system during a warm start cache recovery utilizing a stripe lock data structure. The stripe lock data structure is defined to maintain reservation status of cache lines within data extents that are part of a logical unit or storage volume. A battery backup unit (BBU) stores stripe lock data structure and dirty cache line data of each of the plurality of controllers during a power failure. Using the stripe lock data structure, a delay required for continued processing of I/O requests from one or more host computers following the warm start cache recovery is minimized. Without saving the stripe lock data structure, continued processing of I/O requests from one or more host computers requires reestablishing stripe locks, during the warm start cache recovery, for cache line data saved before the power failure. A computer program product for maintaining cache coherency amongst a plurality of caching storage controllers in a data storage system during a warm start is also provided which includes a computer readable medium and a computer mechanism stored thereon for implementing the inventive method and procedures thereof. Advantages of the invention include eliminating the delay required to re-establish stripe locks in order to flush dirty cache line data to a storage volume during a warm start cache recovery.

Warm start cache recovery in a dual active controller with cache coherency using stripe locks for implied storage volume reservations

The present invention provides a system, apparatus, and method for managing a data storage system in n-way active controller configuration, such that a controller can detect the failure of and reset more than just a single other controller. To accomplish this, a controller sends a ping message to at least a subset of the other controllers, and waits for any of the other controllers to respond to the ping message within a first predetermined amount of time. If any of the other controllers do not respond to the ping message within the first predetermined amount of time, it is determined that the non-responding controller has failed. The controller will reset any failed controller.

System, apparatus, and method for managing a data storage system in an n-way active controller configuration

This inventive provides a multiple level cache structure and multiple level caching method that distributes I/O processing loads including caching operations between processors to provide higher performance I/O processing, especially in a server environment. A method of achieving optimal data throughput by taking full advantage of multiple processing resources is disclosed. A method for managing the allocation of the data caches to optimize the host access time and parity generation is disclosed. A cache allocation for RAID stripes guaranteed to provide fast access times for the XOR engine by ensuring that all cache lines are allocated from the same cache level is disclosed. Allocation of cache lines for RAID levels which do not require parity generation and are allocated in such manner as to maximize utilization of the memory bandwidth is disclosed. Parity generation which is optimized for use of the processor least utilized at the time the cache lines are allocated, thereby providing for dynamic load balancing amongst the multiple processing resources, is disclosed. An inventive cache line descriptor for maintaining information about which cache data pool the cache line resides within, and an inventive cache line descriptor which includes enhancements to allow for movement of cache data from one cache level to another is disclosed. A cache line descriptor with enhancements for tracking the cache within which RAID stripe cache lines siblings reside is disclosed. System, apparatus, computer program product, and methods to support these aspects alone and in combination are also provided.

System, apparatus and method for multi-level cache in a multi-processor/multi-controller environment

System, method and computer program for maintaining cache coherency amongst a plurality of caching storage controllers operating in unison supplying data in response to requests from one or more host computers. The method comprises the steps of defining a reservation data structure to maintain reserved, partial, and full ownership status of data extents that are part of the logical unit or storage volume, and using the reservation data structure to verify that a new update to the data is allowed.

Growing community of inventors

Berthoud, CO, United States of America

Joseph G Skazinski