Crosspoint Solutions, LLC

Harris Corporation

Matrix Semiconductor, Inc.

Advanced Micro Devices Corporation

Sierra Semiconductor

Gatefield Corporation

Joseph G Nolan, Iii

Christopher E Phillips

Michael G Ahrens

Laurence H Cooke

Timothy L Blankenship

Mark G Johnson

Matthew P Crowley

Michael Allen Van Buskirk

John Christian Holst

John M Caywood

Robert J Lipp

Donald A Draper

Te-Long Chiu

Robert U Broze

Ying K Shum

Richard D Freeman

A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.

Charge pump circuit

The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line. The source-grounded transistors and the corresponding sourceless transistors are programmed identically providing substantially the same capacitance load on the bit-line and the bit-bar-line.

High speed dynamic differential logic circuit employing capacitance

A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.

General purpose, non-volatile reprogrammable switch

An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.

Programmable input/output buffer circuit with test capability

An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.

Input-output circuit for increasing immunity to voltage spikes

Multiplexer with level shift capabilities

An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.

In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled 'T'. The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.

Electrically alterable non-volatile memory device

The problem of the distributed voltage drop along a resistive word line through which fusible elements of a circuit array are selectively programmed to a state of high resistance (effective open circuit) is circumvented by incorporated an auxiliary word line driver as part of the array. The auxiliary word line driver is coupled to the word line at a location apart from the main word line driver, so as to reduce the effective resistance and consequential voltage drop along the word line. As a result, for each memory cell along a respective word line there is sufficient 'rupturing current' capability, whereby each fusible element of the memory array may be successfully programmed regardless of its physical location within the array.

Auxiliary word line driver for effectively controlling programmability

A test enabling circuit for actuating specific testing circuitry contained within a programmable device, whereby the test enabling circuit and a portion of the normal operational circuits of the device share a common input pin. Because of the dual functionality of the common input pin, the test enabling circuit is designed to respond to a specified test signal, which is either of an opposing polarity, or of a higher magnitude of the same polarity with respect to the normal operational signal. The enabling circuit includes several IGFET devices arranged such that the noise margin of the enabling circuit may be adapted for accommodating varying environments of noise. ESD circuitry is included to protect the testing and test enabling circuits against electrostatic discharge.

Test enabling circuit for enabling overhead test circuitry in

A testing circuit for testing fuse elements in programmable memory devices. The circuit provides for testing whether the fuses have the proper resistance, both after manufacturing and after programming of the memory device. The testing circuit includes a current varying means which may include either a variable resistance or a variable current sink. The variable resistance is connected to a fuse element to form a voltage divider with the same. A sensing amplifier is connected at a node therebetween for sensing the current through the fuse element and, thus, the resistance of the same. The variable current sink provides variable current levels, thereby achieving the same above results.

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San Jose, CA, United States of America

Joseph G Nolan, Iii