Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Joseph F Orth

Chris M Giles

Gregg Bernard Lesartre

Russ William Herrell

Craig William Warner

John A Morrison

David Charles Hewson

Abdulla M Bataineh

Andrew Ray Wheeler

Jonathan P Beecroft

Andrew Steven Kopser

Anthony M Ford

Trevor Alan Jones

John R Planow

Ryan Akkerman

Bryan D Hornung

Harvey Ray

Daniel V Zilavy

Gerald J Kaufman, Jr

Michael Joseph Phelps

Brian S Birk

The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Distributed storage of packet transformation information in forwarding hardware

A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

Remapping operations

In one example a system includes a memory, and at least one memory controller to: detect a failed first memory location of the memory, remap the failed first location of the memory to a spare second location of the memory based on a pointer stored at the failed first memory location, and wear-level the memory. To wear-level the memory, the memory controller may copy data from the spare second location of the memory to a third location of the memory, and keep the pointer in the failed first memory location.

Memory location remapping and wear-levelling

In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

Write tracking for memories

A method and system for migrating at least one critical resource during a migration of an operative portion of a computer system are disclosed. In at least some embodiments, the method includes (a) sending first information constituting a substantial copy of a first of the at least one critical resource via at least one intermediary between a source component and a destination component. The method further includes (b) transitioning a status of the destination component from being incapable of receiving requests to being capable of receiving requests, and (c) re-programming an abstraction block to include modified addresses so that at least one incoming request signal is forwarded to the destination component rather than to the source component.

Method and system for migrating critical resources within computer systems

One exemplary method of assigning addresses in two or more address spaces with address fields of different lengths comprises defining address types, assigning a value to first bits at the high ends of the address fields to identify a first said address type, assigning second bits at the low ends of the address fields to identify addresses of the first said address type, and inserting different numbers of additional bits between the first bits and the second bits in the two or more address spaces.

Address handling

A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.

Method and system for handling interrupts within computer system during hardware resource migration

Growing community of inventors

Ft. Collins, CO, United States of America

Joseph F Orth