Hrl Laboratories, LLC

Hughes Aircraft Company

Hughes Electronics Corporation

Joseph F Jensen

Jose Cruz-Albrecht

Peter Petre

Albert E Cosand

Gopal Raghavan

Keh-Chung Wang

Michael J Delaney

Daniel Yap

Lawrence E Larson

James Chingwei Li

David H Chow

Adele E Schmitz

Zhiwei A Xu

Yen-Cheng Kuan

Kyung-Ah Son

Ryan G Quarfoth

Donald A Hitko

Mehran Mokhtari

Robert H Walden

Henrik T Jensen

Jeong-Sun Moon

Shubha Kadambo

A reconfigurable optical frequency selective structure having embedded therein:

Electrically-reconfigurable optical device structures with phase change materials

An agile transceiver including a receiver channel that includes an input, a coarse tracking filter coupled to the input, the coarse tracking filter having a set of at least two bandpass filters for filtering signals from the input into at least two coarse pass bands, a mixer coupled to an output of the coarse tracking filter, a selected local oscillator coupled to the mixer for mixing with the output of the coarse tracking filter and shifting a desired coarse pass band to near a base band, a fine tracking filter for filtering the shifted and desired coarse pass band to a fine pass band, and a band pass &#x3a3;&#x394; demodulator for converting signals in the fine pass band from analog into digital. The agile transceiver may include a corresponding transmitter channel.

Agile radio architecture

A method delaying a pulse domain signal using a time encoder circuit and a time encoder based beamformer method and apparatus for use in receiving and/or transmitting applications.

Time encoded circuits and methods and a time encoder based beamformer for use in receiving and transmitting applications

A circuit for generating chaotic signals implemented using heterojunction bipolar transistors (HBTs) and utilized in low probability intercept communications. The HBT chaotic circuit generates truly random analog signals in the GHz range that are non-repeating and deterministic and may not be replicated by preloading a predetermined sequence. A fully differential autonomous chaotic circuit outputs two pairs of chaotic signals to be used in a communication system. As it is impossible to generate identical chaotic signals at the transmitter and receiver sites, the receiver itself sends the chaotic signal to be used for encoding to the transmitter. The receiver includes a chaotic signal generator and digitizes, upconverts, and transmits the generated chaotic signal to the transmitter. The transmitter uses the received chaotic signal to code data to be transmitted. The receiver decodes the transmitted data that is encoded by the chaotic signal to retrieve the transmitted data.

Chaotic signal enabled low probability intercept communication

A highly linear mixer and method for cancelling field effect transistor channel resistance modulation are provided. At least a portion of the voltage of an input signal is added to a drive signal to cancel distortion arising from modulation of the voltage of the input signal.

Highly linear mixer and method for cancelling FET channel resistance modulation

The present invention relates to a digital communication architecture based upon the concept of time encoding. In one aspect, systems provide time-encoding-based digital communication, the systems comprising a transmitter, a communication channel, and a receiver. In another aspect, methods for digital communication comprise time encoding digital input data and then transmitting the resultant asynchronous pulse signal to a receiver that converts the asynchronous pulse signal back into digital symbols. Methods of providing a digital communication link can include (i) providing digital symbols, (ii) time encoding the digital symbols to generate asynchronous pulse signals, (iii) communicating switching times of the signals to a receiver, and (iv) digitizing in parallel and reconstructing the digital symbols. The methods and systems of the invention can utilize existing chip-scale circuit technologies and can be characterized by link capacities of 50 Gbit/sec, 100 Gbit/sec, 200 Gbit/sec, or higher.

Time-encoding-based high-capacity digital communication link

A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.

Analog to digital converter using asynchronous pulse technology

The present invention provides an adaptive, intelligent transform based Analog to Information Converter (AIC) for wideband signals by directly converting an analog signal to information (e.g., features, decisions). This direct conversion is achieved by (i) capturing most of the information of a wideband signal via hardware/software implemented mathematical transformations, (ii) effectively removing unwanted signals such as jammer and interfere from the input signal, and (iii) using novel algorithms for highly accurate decision making and feature extraction (e.g., high probability of detection with low probability of false alarm). The jump in the improvement over today's state-of-the-art is in terms of effective and optimum signal information extraction at high-speed.

Adaptive, intelligent transform-based analog to information converter method and system

An analog to digital converter comprises a plurality of comparators, each comparator for comparing an input electrical signal with a respective, pre-selected reference electrical signal, an encoder coupled to the comparators to receive a detection signal from each comparator indicative of the input signal, and a plurality of reference circuits, each reference circuit coupled to a respective one of the plurality of comparators to supply the respective reference electrical signal to the respective comparator.

Reprogrammable distributed reference ladder for analog-to-digital converters

A Delta-Sigma Analog-to-Digital Converter (ADC) that can have a very high sampling rate (over 100 GHz) and which is preferably optically sampled to help achieve its very high sampling rate. The sampling rate can be many times higher than the regeneration speed of the electronic quantizers used in the ADC.

Time-interleaved delta sigma analog to digital modulator

A method and apparatus for digital-to-analog conversion utilizing randomized dynamic element matching for the attenuation of harmonic distortion during the conversion process due to non-ideal circuit behavior is presented. The present invention introduces a new DEM approach that results in a simplified DAC architecture relative to previous DACs, while preserving optimal spurious-free dynamic range (SFDR). The particular topology utilized involves the use of a bank of DAC-elements, preferably 1-bit DAC elements, the outputs of which are summed to yield a single multiple-level DAC. During each conversion cycle, random selection is used to determine the addresses of the DAC-elements used in order to &ldquo;scramble&rdquo; the DAC noise arising from each individual 1-bit DAC.

Method and apparatus for randomized dynamic element matching DAC

A digital waveform generator reads out simulated .DELTA..SIGMA. ADC data for a desired periodic analog waveform from a memory and converts it, using a low-resolution high speed DAC, into a synthesized analog waveform. The .DELTA..SIGMA. digital waveform generator is preferably designed to take advantage of the natural evolution of device technologies. The memory is fabricated with older technologies, which tend to be slower but have a much higher integration. The DAC is implemented in more recent technologies, which are faster but have less integration. A speed up buffer or buffers in intermediate speed intermediate integration technologies may be included to provide a bridge between the low speed memory and the low integration DAC. As the current technologies become more well developed, and thus more integrated, and new higher speed technologies take their place, the technologies for the various components will gradually change, but the architecture should remain viable and superior to the known digital generators.

Digital waveform generator and method for synthesizing periodic analog

A positive current source (PCS) for supplying common mode current. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply the common mode current (I.sub.cm) while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity. The PCS has a common mode resistance which is small enough to maintain a stable common mode operating point with process variations providing minimal impact.

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Malibu, CA, United States of America

Joseph F Jensen