Intel Corporation

Intel Ndtm US LLC

Sk Hynix Nand Product Solutions Corp.

Joseph F Doller

Kristopher H Gaewsky

Xin Guo

Paul D Ruby

Yogesh B Wakchaure

David J Pelster

Robert Frickey

Robert E Frickey

Justin R Dayacap

Byeongkyu Cho

Noah Mebane

Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.

Read latency reduction for partially-programmed block of non-volatile memory

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

SSD with reduced secure erase time and endurance stress

Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Method and apparatus for reducing read latency for a block erasable non-volatile memory

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El Dorado Hills, CA, United States of America

Joseph F Doller