Motorola Corporation

Other

Motorola Solutions, Inc.

Joseph E Phillips

Randy L Ekl

Anthony R Metke

Aparna Pandey

Christopher G Ware

Mark J Johnson

Michael H Retzer

Scott H Richards

Steven Sanghoon Lee

Walter H Kehler

Mario F Derango

Richard B Meador

John Jeffery Oskorep

Charles Jackson

Anthony J Cecchin

A method and system for data transmission by computational devices in a wireless network () are disclosed. A computational device () organizes the wireless network in a hierarchical topology having at least one root node and updates a list of interferers and a list of descendents. Then, the computational device allocates a Contention Free Period (CFP) slot to each computational device in the wireless network based on at least one of the list of interferers and the list of descendents and transmits data during the allocated CFP slot.

Method and system for data transmission in a wireless network

Techniques are provided for selecting a root node in an ad hoc network comprising a plurality of nodes including a first node. According to one implementation of these techniques, a first node can receive a message from at least one of the other nodes. Each message includes a number of primary factors associated with a particular node regarding capabilities of the particular node. The primary factors associated with each node can then be evaluated, and an attempt can be made to select the root node based on the primary factors associated with each node. If the first node is unable to select the root node based on the primary factors associated with each node, then the root node can be selected based on secondary factors associated with each node.

Method and apparatus for root node selection in an ad hoc network

Techniques are provided for selecting a root node in an ad hoc network that contains a plurality of nodes including a first node. According to one implementation of these techniques, a first node can receive a message from at least one of the other nodes. Each message includes a number of primary factors associated with a particular node regarding capabilities of the particular node. The primary factors associated with each node can then be evaluated, and an attempt can be made to select the root node based on the primary factors associated with each node. If the first node is unable to select the root node based on the primary factors associated with each node, then the root node can be selected based on secondary factors associated with each node.

Method and apparatus for omniscient root node selection in an ad hoc network

A method and apparatus for improving throughput in a wireless local area (WLAN), which includes buffering a set of messages, identifying a target address for the set of messages, and concatenating the set of messages based on the target address. The target address can be either unicast, broadcast, multicast or combination of unicast, broadcast and multicast as described herein.

Method and apparatus for improving throughput in a wireless local area network

In one embodiment of the present invention, an access point () receives a multicast packet intended for a particular multicast group. Upon receipt, the access point only rebroadcast the multicast packet over a wireless segment if it determines that there is at least one wireless subscriber unit () belonging to the particular multicast group and associated with the access point that did not originate the multicast packet. Optionally, if the multicast packet signals an automatic rebroadcast of the multicast packet over the wireless segment, the access point automatically rebroadcasts the multicast packet without determining whether there is at least one wireless subscriber unit belonging to the particular multicast group and associated with the access point that did not originate the multicast packet.

Method for preserving wireless resources in a wireless local area network

In accordance with the present invention, a charging device ( ) is capable of receiving a first device ( ) coupled to a second device ( ). The first device has a first battery associated therewith and the second device has a second battery associated therewith. The charging device is capable of charging the first battery and the second battery in one of the following manners: charging the first and second batteries in a serial manner, charging the first and second batteries in a parallel manner, and charging the second battery from the energy stored in the first battery.

Charging device for charging a plurality of devices

A radio (100) having an integrated transceiver circuit (102) avoids circuit crosstalk through the use of a clock shifter circuit (120). The radio includes a microcontroller unit (MCU) (104) controlled by a MCU clock. A channel selector (116) coupled to the MCU (104) provides a selected frequency channel while memory (106) downloads channel information which includes integer clock shifter ratios assigned to each channel. The integrated transceiver (102) includes a clock shifter circuit (120) which divides a reference signal into a clock frequency and provides this clock frequency to the MCU (104) as the MCU clock. The MCU (104) reprograms the clock shifter circuit (120) with one of the integer clock shifter ratios to generate a shifted MCU clock frequency if the selected frequency channel is susceptible to harmonics of the MCU clock.

Apparatus for clock shifting in an integrated transceiver

A radio transceiver system (100) includes an option board interface (117) with an analog interface (119) and a digital interface (125). Option board interface (117) is used for conveying information between an optional memory board (133) and a digital processing unit (105). Option board interface (117) also controls analog audio functions through analog interface (119). Option board interface (117) enhances functional operation of the radio transceiver system (100) by allowing options to be selected which are not provided as standard radio equipment.

Radio having an option board interface and an option board for use

An apparatus for and method of scanning a key array (101-116) uses two or three scan lines (134 and 135 or 308, 309, and 310), thereby limiting the need for an excessive number of input/output lines of a processor (136). A separate resistor ladder (301,302, 303) is provided for each dimension of keys, including row, column, and/or matrix. A minimal number of parts is also required to implement the resistor ladder (301,302, 303). A reference conductor (311), a row conductor (312), a column conductor (313), and, if desired, a matrix conductor (314) each run under each key, such that when a different key is depressed, a unique combination of voltages appears at the scan lines (134 and 135 or 308, 309, and 310) for the resistor ladders (301, 302, 303).

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Huntley, IL, United States of America

Joseph E Phillips