General Electric Company

Joseph E Krisciunas

Donald Thomas McGrath

Steven L Garverick

Mark Fredrick Culler

Philippe L Jacob

Karl D Pedersen

Lisa E Rosner

Veronica Kertesz

Jonathan A Wolf

Karanam Rajaiah

A communication bus containing master and slave devices includes a monitor unit for fault tolerant communications. In the event the master is unable to communicate, the monitor automatically assumes the master communication role. When more than one monitor is connected within the communications network, the monitor with the lowest communications address assumes the master communications role. The master includes software implementation that allows an operator to obtain data from any of the slave devices via the monitor.

Fault tolerant communication monitor for a master/slave system

A memory storage verification device for use with a memory storage unit in which electrical signals stored in selected memory locations are periodically accessed by an external processor. The device includes a register for storing the address of a memory location in the memory storage unit having a stored electrical signal, a comparator for comparing the address stored in the register with an electrical signal from the memory storage unit providing the address of the memory location being accessed by the external processor, and a latch including a trigger coupled to the output port of the comparator. The input port of the latch is coupled to the memory storage unit and receives the electrical signal stored in the memory location being accessed when the trigger receives a signal from the comparator.

Memory storage verification system for use in an integrated circuit for

A programmable length decimation filter responsive to an externally derived stream of quantized electrical signals arriving at a predetermined rate comprises a counter, a resolution filter, and an accumulator. The resolution filter is responsive to the counter output signals, to an externally derived resolution select signal, and to the stream of quantized signals, and operates to mask selected quantized signals in order to provide resolution filter output signals to the accumulator on a plurality of resolution filter output ports. The resolution select signal allows for providing flexibility of operation regarding the tradeoff of the bandwidth of the decimation filter with its resolution capability.

Programmable length decimation filter as for sigma-delta modulators

A system for processing digital electrical power signals derived from at least one externally supplied, substantially continuous, substantially alternating, electrical signal having a primary or fundamental frequency, comprises: a multiply-accumulate arithmetic processor having three input ports with at least one input port for receiving the digital electrical power signals, an output port and a processor control port; a first memory unit for storing a plurality of processor control signals; a second and third memory unit each for storing a separate plurality of processor input signals; and a memory control unit having the capability to respectively couple the first memory unit to the processor control port, and the first processor input port to one of the second and third memory units for each cycle of the primary frequency so that newly received digital electrical power signals may be continually processed by the processor for a predetermined number of cycles.

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Clifton Park, NY, United States of America

Joseph E Krisciunas