Hughes Aircraft Company

Other

Data General Corporation

Joseph E Farb

Chen-Chi P Chang

Maw-Rong Chin

Mei F Li

Kuan Y Liao

Jerry S Wang

Robert C Fang

Chung Hsu

C P Chang

Victor Liang

Maw R Chin

A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions. This portion of the method comprises the steps of forming maskless self-aligned gate metallization, forming maskless self-aligned contacts to the gate metallization and filling the trench, forming source metallization, and forming a drain contact on the substrate. The method employs a single minimum geometry trench mask. The key features of the transistors are defined by the trench mask and related processing parameters. Because of the self-alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded gate junction.

Method of making a self-aligned static induction transistor

A solid state triode employs the Hall effect to asymmetrically proportion flow of current through different branches of a number of cascaded bifurcated N- charge carrier channels (10,18,20), thereby providing an indication of strength and direction of an applied magnetic field by measuring magnitude and sense of the difference between currents flowing in the two channel branches (14,16,24,26,30,32). The solid state triode is formed on an silicon-on-insulator (SOI) substrate (47,48,49) in which an N+ source region (54) and at least two end N+ drain regions (56,58) are interconnected by an N- charge carrier channel (60) that is defined by a plurality of P+ regions (64a,64b,64c,64d) in a thin single crystal silicon substrate (49) between the source and drain regions (54,56,58). A polysilicon gate (52) overlies the N- channel and acts as a self-aligning mask during manufacture of the triode to precisely align the N+ and P+ doping to the polysilicon gate configuration. The SOI has a very thin N- doped layer to which the N+ and P+ doping is applied in steps of successively different energy levels so that the doping extends completely through the N- layer and is uniform throughout the thickness of the layer. The N- channel is narrow and has a width at least twice the thickness of the crystal silicon uppermost layer of the SOI substrate.

Magnetic field detection

A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.

Method of making FET with two reverse biased junctions in drain region

Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d).

Flash EEPROM cell and array with bifurcated floating gates

Field-effect transistor with structure for suppressing hot-electron

A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride. The polysilicon mask is etched to expose the gate metal disposed on the field. A second layer of metal is deposited to make contact with the source and gate regions. A passivation layer is formed, and interconnection pads are formed that connect the first and second layers of metal. The present method employs a single minimum geometry trench mask. The key features of the transistor are defined by the trench mask and related processing parameters. Because of the self alignment achieved by the present invention, the number of channels per unit area is higher, which results in higher transconductance. In addition, some of the parasitic capacitance is eliminated by the present invention, resulting in faster operational speed. The variable sidewall trench oxide thickness allows fabrication of static induction transistors with higher or lower breakdown voltages according to the thickness that is chosen, and for a more graded P gate junction.

Method of making a self aligned static induction transistor

Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.

Control of backgate bias for low power high speed CMOS/SOI devices

Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures. The protective layers are then removed by a wet etching procedure. The semiconductor device is fabricated to completion in a conventional manner thereafter. In the second method, a nitride layer is deposited over the mesa structures and thermal oxide layer. A thin oxide layer, which is generally deposited by means of a chemical vapor deposition procedure, is deposited over the silicon nitride layer. The formed structure is then processed to expose the N-channel mesa structures. This is accomplished using an N-well mask, the oxide layer is etched to expose the silicon nitride layer over the N-channel, and the nitride layer covering the N-channel is removed by means of hot phosphoric acid using the oxide layer as a mask. The doping layer is then deposited over the mesa structures. This doping layer is then heated to drive the dopant/implant into the edges of the N-channel mesa structures. The doping layer is then removed by wet oxide etching, the nitride layer is removed by rinsing in hot phosphoric acid and the thermal oxide layer is removed by a wet oxide etching procedure. The semiconductor device is again fabricated to completion in a conventional manner thereafter.

Edge doping processes for mesa structures in SOS and SOI devices

A method for making metal gate MOS capacitors with standard silicon gates processes, including the steps of providing a semiconductor substrate and defining active areas and capacitor areas therein, forming field oxide regions that generally surround the active areas and the capacitor areas, forming a gate oxide layer over the active areas and the capacitor areas, and forming polysilicon gates over the active areas. Highly doped source and drain regions in the active areas and highly doped bottom capacitor plate regions in the capacitor areas are then formed, and blanket oxide layer is deposited over the semiconductor structure. The capacitor areas are opened to expose the highly doped bottom capacitor plate regions, and the semiconductor structure is heated to reflow the deposited oxide layer and to grow a capacitor oxide layer over the exposed capacitor areas.

Metal gate capacitor fabricated with a silicon gate MOS process

A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.

Method of making a latch up free, high voltage, CMOS bulk process for

A process is disclosed for filling contact or via openings in an integrated circuit with electrically conductive plugs. The process includes the steps of (a) forming one or more openings in an planarized oxide layer, where the one or more openings is disposed over and exposes semi-insulating or conductive regions, and (b) filling the one or more openings with conductive material to substantially the same level as the adjacent surfaces of the oxide layer to form respective planarized conductive plugs. A further aspect of the invention is directed to a process which includes the steps of (a) forming first one or more openings of a first predetermined depth in a planarized oxide layer, the first one or more openings being disposed over the exposing respectively associated semi-insulating or conductive regions; (b) partially filling the first one or more openings with conductive material to a level corresponding to a second predetermined depth; (c) forming second one or more openings of the second predetermined depth in the planarized oxide layer, the second one or more openings being disposed over the exposing respectively associated semi-insulating or conductive regions; and (d) filling the first and second one or more openings to substantially the same level to form respective planarized plugs in the opeinings.

Conductive plug for contacts and vias on integrated circuits

A method of forming CMOS transistors with self-aligned field regions. First and second spaced apart areas are provided on a silicon substrate. A masking member is formed protecting the first of said areas and exposing the second. The exposed area is doped with a p-type material which is driven in to form a p-well. The same region is again doped with additional p-type material after which the CMOS transistors are fabricated.

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Riverside, CA, United States of America

Joseph E Farb