International Business Machines Corporation

Joseph E Eckelman

Otto Andreas Torreiter

David T Hui

Phong T Tran

Thomas J Knips

Donato Orazio Forlenza

Orazio Pasquale Forlenza

Ulrich Baur

Franco Motika

Gary William Maier

Richard Frank Rizzolo

Phillip J Nigh

Bryan J Robbins

Robert Benjamin Gass

William James Hurley

Kevin C Gotze

Thomas G Foote

Steven Michnowski

Rocco E DeStefano

James A Kyle

Jennifer Yuk Sim Yan

A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.

AC ABIST diagnostic method, apparatus and program product

This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

Automated system and processing for expedient diagnosis of broken shift registers latch chains

System-accessible frequency measuring circuits and procedures permit on-chip testing of the oscillators and provide test results observable off chip via LSSD scan paths. This allows a rapid ensemble of ring oscillators in a standard ASIC test flow without the need for on chip analog test equipment (the test apparatus has effectively been created on device and can be digitally configured, operated and read). Frequency measuring logic that can 1) functionally operate to measure the frequency of the ring oscillators; 2) participate in traditional logical tests such as LSSD and LBIST to verify that the circuit is manufactured correctly and is likely to operate and 3) operate in a special ring-oscillator test mode, that allows the logic to operate on a tester very similarly to the way it does functionally. In this mode, the frequency measuring logic can be scanned to a specific state, started by pulsing a digital I/O, and the measured analog value can be scanned out sometime later after the test has completed. Test interrogations are distributed on-chip through an LSSD shift register chain to individually evaluate each of a plurality of the oscillators.

Analog testing of ring oscillators using built-in self test apparatus

A method for real time capture of the desired failing chip cell diagnostic information from high speed testing of a semiconductor chip with on chip LSSD registers having built in self test functions and a fail trap register, and there is provided a programmable skip fail counter, and a hold and compare function circuit. The programmable skip counter is enabled for initialization to a 'record first fail' mode, and then with non-zero values of the skip counter to a 'record next fail' mode with scan initialization of the LSSD registers of the semiconductor chip. The diagnostic information for the chip is obtained by collecting data from scanning the circuits of said semiconductor chip for a failing cell for immediate scan-out off-chip at a level of assembly test.

Method and apparatus for ABIST diagnostics

The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages ( ) of a semiconductor chip. Two dedicated support transistor devices ( ) are added into the prior art switching scheme, together with a simple control logic ( ) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver ( ) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Self-test for leakage current of driver/receiver stages

An exemplary embodiment of the invention is a method for LBIST testing integrated circuit. The method includes generating a plurality of multi-bit test patterns and grouping the multi-bit test patterns by a plurality of test pattern partitions including a first test pattern partition having a first number of bits and a second test pattern partition having second number of bits greater than the first number. The first test pattern partition is applied to the integrated circuit to generate a first signature that is compared to a first reference signature to detect a failure. The second test pattern partition is applied to the integrated circuit to generate a second signature that is compared to a second reference signature to detect a failure in the integrated circuit.

Method and system for determining repeatable yield detractors of integrated circuits

The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type ( ) and N-type ( ), respectively, are split into at least two sub-devices P , P and N , N , and are controlled separately by a control logic ( ). Then, for example N is used for testing the P device, and P is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Self-test with split, asymmetric controlled driver output stage

Growing community of inventors

Hopewell Junction, NY, United States of America

Joseph E Eckelman